diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-04-18 17:01:01 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-04-21 23:14:45 +0000 |
| commit | 6d3b7e6f627989ed96de3576a6b19878eb2220a5 (patch) | |
| tree | 3e627466630e810950aa2ab88ab8135482edf50b | |
| parent | b3282093308d62c4fc3e6bf4e4183d2bd01bb09f (diff) | |
| download | coreboot-6d3b7e6f627989ed96de3576a6b19878eb2220a5.tar.xz | |
soc/amd/stoneyridge: Fix gnvs aoac initialization
Correct the SD and SATA assignments.
TEST=Boot Grunt
BUG=b:130788333
Change-Id: Ib75e1dbb0cd7f90a8d297d11d3a7c3bad47a8d21
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 2f32c5c86e..9c546947e3 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -927,9 +927,9 @@ static void set_sb_final_nvs(void) gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); /* Rely on these being in sync with devicetree */ sd = pcidev_path_on_root(SD_DEVFN); - gnvs->aoac.st_e = sd && sd->enabled ? 1 : 0; + gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; sata = pcidev_path_on_root(SATA_DEVFN); - gnvs->aoac.sd_e = sata && sata->enabled ? 1 : 0; + gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; gnvs->aoac.espi = 1; amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); |