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| author | Raul E Rangel <rrangel@chromium.org> | 2020-06-17 11:10:58 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-22 11:51:56 +0000 |
| commit | 6f1d35e72dcc0d2ded8c5ebe15d8d9cf9c9ba5cb (patch) | |
| tree | c56495ac1c8a83ca2e6d3c92e142d884bc814e3f | |
| parent | ec26428fcfb4b255d51f43597f7446f6f2f03daf (diff) | |
| download | coreboot-6f1d35e72dcc0d2ded8c5ebe15d8d9cf9c9ba5cb.tar.xz | |
soc/amd/picasso/bootblock: Clear BSS section
We are currently relying on the assumption that the amdcompress tool
will zero out the bss section. Instead of relying on this assumption,
lets explicitly clear it.
The implementation was copied from assembly_entry.S.
BUG=b:147042464
TEST=Cold boot trembyle and also s3 resume trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb4f4cc6932dd4c3c92d4e7647569f9a0c69ea4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/amd/picasso/bootblock/pre_c.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/bootblock/pre_c.S b/src/soc/amd/picasso/bootblock/pre_c.S index 83e5491cd5..6fae1ed1cb 100644 --- a/src/soc/amd/picasso/bootblock/pre_c.S +++ b/src/soc/amd/picasso/bootblock/pre_c.S @@ -23,6 +23,15 @@ bootblock_resume_entry: bootblock_pre_c_entry: post_code(0xa0) + /* Clear .bss section */ + cld + xor %eax, %eax + movl $(_ebss), %ecx + movl $(_bss), %edi + sub %edi, %ecx + shrl $2, %ecx + rep stosl + movl $_eearlyram_stack, %esp /* Align the stack and keep aligned for call to bootblock_c_entry() */ |