DMP Vortex86ex board & chip: Remove - using LATE_CBMEM_INIT

All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.

If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.

chips:
soc/dmp/vortex86ex

Mainboards:
mainboard/dmp/vortex86ex

Change-Id: Iee7b6005cc2964b2346aaf4dbd9b2d2112b7403f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

32 files changed, 0 insertions, 4456 deletions

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
index 46e541962b..72fc29c1e0 100644
--- a/src/cpu/Makefile.inc
+++ b/src/cpu/Makefile.inc
@@ -3,7 +3,6 @@
 ################################################################################
 subdirs-y += allwinner
 subdirs-y += amd
-subdirs-y += dmp
 subdirs-y += armltd
 subdirs-y += imgtec
 subdirs-y += intel
diff --git a/src/cpu/dmp/Kconfig b/src/cpu/dmp/Kconfig
deleted file mode 100644
index aabaf05075..0000000000
--- a/src/cpu/dmp/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-source src/cpu/dmp/vortex86ex/Kconfig
diff --git a/src/cpu/dmp/Makefile.inc b/src/cpu/dmp/Makefile.inc
deleted file mode 100644
index a5fb5b6fe0..0000000000
--- a/src/cpu/dmp/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-subdirs-$(CONFIG_CPU_DMP_VORTEX86EX) += vortex86ex
diff --git a/src/cpu/dmp/dmp_post_code.h b/src/cpu/dmp/dmp_post_code.h
deleted file mode 100644
index 4a61c9a94c..0000000000
--- a/src/cpu/dmp/dmp_post_code.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef DMP_POST_CODE_H
-#define DMP_POST_CODE_H
-
-/* DMP Vortex86EX specific POST codes */
-
-#define POST_DMP_KBD_FW_UPLOAD			0x06
-#define POST_DMP_KBD_CHK_READY			0x07
-#define POST_DMP_KBD_IS_READY			0x08
-#define POST_DMP_KBD_IS_BAD			0x09
-#define POST_DMP_KBD_FW_VERIFY_ERR		0x82
-#define POST_DMP_ID_ERR				0x85
-#define POST_DMP_DRAM_TEST_ERR			0x86
-#define POST_DMP_DRAM_SIZING_ERR		0x77
-
-#endif /* DMP_POST_CODE_H*/
diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig
deleted file mode 100644
index 1af7ec4bf8..0000000000
--- a/src/cpu/dmp/vortex86ex/Kconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-config CPU_DMP_VORTEX86EX
-	bool
-
-if CPU_DMP_VORTEX86EX
-
-config CPU_SPECIFIC_OPTIONS
-	def_bool y
-	select ARCH_BOOTBLOCK_X86_32
-	select ARCH_VERSTAGE_X86_32
-	select ARCH_ROMSTAGE_X86_32
-	select ARCH_RAMSTAGE_X86_32
-	select UDELAY_TSC
-
-# ROM Strap PLL config setting :
-
-choice
-	prompt "ROM Strap PLL config"
-	default PLL_300_300_33
-
-config PLL_200_200_33
-	bool "CPU=200Mhz/DRAM=200Mhz/PCI=33Mhz"
-
-config PLL_300_300_33
-	bool "CPU=300Mhz/DRAM=300Mhz/PCI=33Mhz"
-
-config PLL_300_300_100
-	bool "CPU=300Mhz/DRAM=300Mhz/PCI=100Mhz"
-
-config PLL_400_200_33
-	bool "CPU=400Mhz/DRAM=200Mhz/PCI=33Mhz"
-
-config PLL_400_200_100
-	bool "CPU=400Mhz/DRAM=200Mhz/PCI=100Mhz"
-
-config PLL_400_400_33
-	bool "CPU=400Mhz/DRAM=400Mhz/PCI=33Mhz"
-
-config PLL_500_250_33
-	bool "CPU=500Mhz/DRAM=250Mhz/PCI=33Mhz"
-
-config PLL_500_500_33
-	bool "CPU=500Mhz/DRAM=500Mhz/PCI=33Mhz"
-
-config PLL_400_300_33
-	bool "CPU=400Mhz/DRAM=300Mhz/PCI=33Mhz"
-
-config PLL_400_300_100
-	bool "CPU=400Mhz/DRAM=300Mhz/PCI=100Mhz"
-
-config PLL_444_333_33
-	bool "CPU=444Mhz/DRAM=333Mhz/PCI=33Mhz"
-
-config PLL_466_350_33
-	bool "CPU=466Mhz/DRAM=350Mhz/PCI=33Mhz"
-
-config PLL_500_375_33
-	bool "CPU=500Mhz/DRAM=375Mhz/PCI=33Mhz"
-
-endchoice
-
-endif
diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc
deleted file mode 100644
index 6b4d0ba74e..0000000000
--- a/src/cpu/dmp/vortex86ex/Makefile.inc
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
-
-bootblock-y += biosdata.ld
-bootblock-y += biosdata_ex.ld
-bootblock-y += biosdata.S
-bootblock-y += biosdata_ex.S
-
-ROMCCFLAGS := -mcpu=i386 -O2
diff --git a/src/cpu/dmp/vortex86ex/biosdata.S b/src/cpu/dmp/vortex86ex/biosdata.S
deleted file mode 100644
index 0441f4fd0a..0000000000
--- a/src/cpu/dmp/vortex86ex/biosdata.S
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-	.section ".dmp_reserved", "a", @progbits
-
-	.skip 0x3c000 - 0x3bc00, 0xff
-
-.previous
-
-	.section ".dmp_kbd_fw_part2", "a", @progbits
-
-	.skip 0x3d000 - 0x3c000, 0xff
-
-.previous
-
-	.section ".dmp_mtbf_low_cnt", "a", @progbits
-
-	.skip 0x3e000 - 0x3d000, 0xff
-
-.previous
-
-	.section ".dmp_kbd_fw_part1", "a", @progbits
-
-	#include "dmp_kbd_fw_part1.inc"
-
-.previous
-
-	.section ".dmp_spi_flash_disk_driver", "a", @progbits
-
-	.skip 0x3f800 - 0x3f000, 0xff
-
-.previous
-
-	.section ".dmp_frontdoor", "a", @progbits
-
-	.skip 0x3fd00 - 0x3f800, 0xff
-
-.previous
-
-	.section ".dmp_isoinfo", "a", @progbits
-
-	.skip 26 * 16, 0xff
-
-.previous
-
-	.section ".dmp_isodata_checksum", "a", @progbits
-
-	.skip 8, 0xff
-
-.previous
-
-	.section ".dmp_mac", "a", @progbits
-
-	.skip 6, 0xff
-
-.previous
-
-	.section ".dmp_mtbf_limit", "a", @progbits
-
-	.skip 3, 0xff
-
-.previous
-
-	.section ".dmp_isodata", "a", @progbits
-
-	.skip 32, 0xff
-
-.previous
diff --git a/src/cpu/dmp/vortex86ex/biosdata.ld b/src/cpu/dmp/vortex86ex/biosdata.ld
deleted file mode 100644
index 8d5f0208e0..0000000000
--- a/src/cpu/dmp/vortex86ex/biosdata.ld
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-SECTIONS {
-
-	/* Vortex86 ROM fixed data areas used range is too big, we need
-	 * to move bootblock from default address to another place,
-	 * otherwise .dmp_frontdoor section can't be included.
-	 * Address before ..fbc00 is available.
-	 */
-	ROMLOC_MIN = 0xffffbc00 - (_erom - _rom + 16) -
-		(CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
-
-	. = 0xffffbc00;
-	.dmp_reserved (.): {
-		KEEP(*(.dmp_reserved))
-	}
-
-	. = 0xffffc000;
-	.dmp_kbd_fw_part2 (.): {
-		KEEP(*(.dmp_kbd_fw_part2))
-	}
-
-	. = 0xffffd000;
-	.dmp_mtbf_low_cnt (.): {
-		KEEP(*(.dmp_mtbf_low_cnt))
-	}
-
-	. = 0xffffe000;
-	.dmp_kbd_fw_part1 (.): {
-		KEEP(*(.dmp_kbd_fw_part1))
-	}
-
-	. = 0xfffff000;
-	.dmp_spi_flash_disk_driver (.): {
-		KEEP(*(.dmp_spi_flash_disk_driver))
-	}
-
-	. = 0xfffff800;
-	.dmp_frontdoor (.): {
-		KEEP(*(.dmp_frontdoor))
-	}
-
-	. = 0xfffffe00;
-	.dmp_isoinfo (.): {
-		KEEP(*(.dmp_isoinfo))
-	}
-
-	. = 0xffffffa0;
-	.dmp_isodata_checksum (.): {
-		KEEP(*(.dmp_isodata_checksum))
-	}
-
-	. = 0xffffffb0;
-	.dmp_mac (.): {
-		KEEP(*(.dmp_mac))
-	}
-
-	. = 0xffffffb8;
-	.dmp_mtbf_limit (.): {
-		KEEP(*(.dmp_mtbf_limit))
-	}
-
-	. = 0xffffffc0;
-	.dmp_isodata (.): {
-		KEEP(*(.dmp_isodata))
-	}
-}
diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S
deleted file mode 100644
index 6686bb7467..0000000000
--- a/src/cpu/dmp/vortex86ex/biosdata_ex.S
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-PLL Freq = 25 * NS /(MS * 2^RS)
-CPU Freq = PLL/(CPU_DIV+2)
-DRAM Freq = PLL/2(DRAM_DIV+1)
-
-DDR3
-CPU/DRAM/PCI            B6 B7 BB BC BD BF
-200/200/33              30 03 0F 02 8F 07
-300/300/33              48 03 0F 02 1F 07
-300/300/33              48 03 0F 3A DF 07          ; write leveling disable, CPU bypass disable
-300/300/33              48 03 0F 22 3F 07          ; CPU bypass disable
-300/300/100             48 03 23 02 7F 07
-400/200/33              60 43 0F 02 3F 07          ; without 200MHz timing, so set 300MHz timing
-400/200/100             60 43 23 02 4F 07
-400/400/33              60 03 0F 02 BF 09
-500/250/33              50 42 0F 02 DF 07
-500/500/33              78 03 0F 02 4F 09
-400/300/33              90 53 0F 02 3F 07
-400/300/33              90 53 0F 1A DF 07          ; write leveling/gate training disable
-400/300/100             90 53 23 02 9F 07
-444/333/33              A0 53 0F 02 5F 08
-466/350/33              A8 53 0F 02 DF 09
-500/375/33              B4 53 0F 02 AF 09
-*/
-
-#if IS_ENABLED(CONFIG_PLL_200_200_33)
-	// 200/200/33              30 03 0F 02 8F 07
-	byte_fffb6 = 0x30
-	byte_fffb7 = 0x03
-	byte_fffbb = 0x0f
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x07
-#elif IS_ENABLED(CONFIG_PLL_300_300_33)
-	// 300/300/33              48 03 0F 02 1F 07
-	byte_fffb6 = 0x48
-	byte_fffb7 = 0x03
-	byte_fffbb = 0x0f
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x07
-#elif IS_ENABLED(CONFIG_PLL_300_300_100)
-	// 300/300/100             48 03 23 02 7F 07
-	byte_fffb6 = 0x48
-	byte_fffb7 = 0x03
-	byte_fffbb = 0x23
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x07
-#elif IS_ENABLED(CONFIG_PLL_400_200_33)
-	// 400/200/33              60 43 0F 02 3F 07          ; without 200MHz timing, so set 300MHz timing
-	byte_fffb6 = 0x60
-	byte_fffb7 = 0x43
-	byte_fffbb = 0x0f
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x07
-#elif IS_ENABLED(CONFIG_PLL_400_200_100)
-	// 400/200/100             60 43 23 02 4F 07
-	byte_fffb6 = 0x60
-	byte_fffb7 = 0x43
-	byte_fffbb = 0x23
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x07
-#elif IS_ENABLED(CONFIG_PLL_400_400_33)
-	// 400/400/33              60 03 0F 02 BF 09
-	byte_fffb6 = 0x60
-	byte_fffb7 = 0x03
-	byte_fffbb = 0x0f
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x09
-#elif IS_ENABLED(CONFIG_PLL_500_250_33)
-	// 500/250/33              50 42 0F 02 DF 07
-	byte_fffb6 = 0x50
-	byte_fffb7 = 0x42
-	byte_fffbb = 0x0f
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x07
-#elif IS_ENABLED(CONFIG_PLL_500_500_33)
-	// 500/500/33              78 03 0F 02 4F 09
-	byte_fffb6 = 0x78
-	byte_fffb7 = 0x03
-	byte_fffbb = 0x0f
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x09
-#elif IS_ENABLED(CONFIG_PLL_400_300_33)
-	// 400/300/33              90 53 0F 02 3F 07
-	byte_fffb6 = 0x90
-	byte_fffb7 = 0x53
-	byte_fffbb = 0x0f
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x07
-#elif IS_ENABLED(CONFIG_PLL_400_300_100)
-	// 400/300/100             90 53 23 02 9F 07
-	byte_fffb6 = 0x90
-	byte_fffb7 = 0x53
-	byte_fffbb = 0x23
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x07
-#elif IS_ENABLED(CONFIG_PLL_444_333_33)
-	// 444/333/33              A0 53 0F 02 5F 08
-	byte_fffb6 = 0xa0
-	byte_fffb7 = 0x53
-	byte_fffbb = 0x0f
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x08
-#elif IS_ENABLED(CONFIG_PLL_466_350_33)
-	// 466/350/33              A8 53 0F 02 DF 09
-	byte_fffb6 = 0xa8
-	byte_fffb7 = 0x53
-	byte_fffbb = 0x0f
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x09
-#elif IS_ENABLED(CONFIG_PLL_500_375_33)
-	// 500/375/33              B4 53 0F 02 AF 09
-	byte_fffb6 = 0xb4
-	byte_fffb7 = 0x53
-	byte_fffbb = 0x0f
-	byte_fffbc = 0x02
-	byte_fffbe = 0xff
-	byte_fffbf = 0x09
-#else
-	#error Error Strap PLL config.
-#endif
-
-tmp_sum = byte_fffb6 + byte_fffb7 + byte_fffbb + byte_fffbc
-pll_checksum = ((tmp_sum >> 8) & 0x3) + ((tmp_sum >> 4) & 0x0f) + (tmp_sum & 0x0f)
-
-byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f
-
-	.section ".a9123_crossbar_config", "a", @progbits
-
-	.skip 0x3fdf0 - 0x3fd00, 0xff
-
-.previous
-
-	.section ".a9123_strap_1", "a", @progbits
-
-	.byte byte_fffb6, byte_fffb7
-
-.previous
-
-	.section ".a9123_strap_2", "a", @progbits
-
-	.byte byte_fffbb, byte_fffbc, byte_fffbd, byte_fffbe, byte_fffbf
-
-.previous
diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.ld b/src/cpu/dmp/vortex86ex/biosdata_ex.ld
deleted file mode 100644
index 04e23c3faf..0000000000
--- a/src/cpu/dmp/vortex86ex/biosdata_ex.ld
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-SECTIONS {
-	. = 0xfffffd00;
-	.a9123_crossbar_config (.): {
-		KEEP(*(.a9123_crossbar_config))
-	}
-
-	. = 0xffffffb6;
-	.a9123_strap_1 (.): {
-		KEEP(*(.a9123_strap_1))
-	}
-
-	. = 0xffffffbb;
-	.a9123_strap_2 (.): {
-		KEEP(*(.a9123_strap_2))
-	}
-}
diff --git a/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc b/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc
deleted file mode 100644
index 302b0cb3ad..0000000000
--- a/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc
+++ /dev/null
@@ -1,527 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-	.byte  0x02, 0x04, 0xa3, 0x02, 0x0a, 0xfb, 0xef, 0x75
-	.byte  0xf0, 0x03, 0xa4, 0xff, 0xae, 0x07, 0x1f, 0xee
-	.byte  0x70, 0xfa, 0x22, 0x02, 0x0a, 0xd5, 0x12, 0x09
-	.byte  0x5e, 0x7f, 0x30, 0x12, 0x05, 0xfb, 0x90, 0xe0
-	.byte  0x00, 0x74, 0x16, 0xf0, 0x12, 0x0d, 0xda, 0xc2
-	.byte  0x92, 0xc2, 0x93, 0xc2, 0x90, 0xd2, 0x91, 0xd2
-	.byte  0xb8, 0xd2, 0xba, 0xd2, 0x88, 0xd2, 0xa8, 0xd2
-	.byte  0x8a, 0xd2, 0xaa, 0x7d, 0x44, 0xe4, 0xff, 0x12
-	.byte  0x0e, 0x3a, 0x7d, 0x4d, 0x0f, 0x12, 0x0e, 0x3a
-	.byte  0x7d, 0x26, 0x0f, 0x12, 0x0e, 0x3a, 0x7d, 0x50
-	.byte  0x0f, 0x12, 0x0e, 0x3a, 0x12, 0x0e, 0x59, 0xd2
-	.byte  0xaf, 0x7f, 0xb1, 0x12, 0x0e, 0xf5, 0x90, 0x0f
-	.byte  0xfe, 0xe4, 0x93, 0xff, 0xb4, 0x55, 0x0a, 0xa3
-	.byte  0xe4, 0x93, 0xb4, 0xaa, 0x04, 0xd2, 0x08, 0x80
-	.byte  0x10, 0xef, 0xb4, 0x12, 0x0c, 0x90, 0x0f, 0xff
-	.byte  0xe4, 0x93, 0xb4, 0x34, 0x04, 0xc2, 0x08, 0xc2
-	.byte  0x12, 0x12, 0x03, 0x6c, 0x12, 0x0d, 0xa6, 0x12
-	.byte  0x01, 0x08, 0x30, 0x01, 0x27, 0x30, 0x12, 0x1f
-	.byte  0x20, 0x00, 0x1c, 0x30, 0x11, 0x19, 0x12, 0x0d
-	.byte  0x25, 0x12, 0x09, 0xc4, 0x30, 0x08, 0x05, 0xc2
-	.byte  0x1a, 0x12, 0x0a, 0x26, 0x12, 0x0d, 0x92, 0xd2
-	.byte  0x00, 0x12, 0x0d, 0x3b, 0x12, 0x07, 0xc2, 0x12
-	.byte  0x0d, 0xda, 0xc2, 0x01, 0x12, 0x03, 0x6c, 0x12
-	.byte  0x07, 0x2e, 0x30, 0x12, 0xc4, 0x30, 0x00, 0xc1
-	.byte  0x90, 0xd0, 0x00, 0xe0, 0x30, 0xe0, 0xba, 0xc2
-	.byte  0xaf, 0x12, 0x0e, 0x07, 0x50, 0x0e, 0x12, 0x0e
-	.byte  0xb6, 0x12, 0x0e, 0xbc, 0xd2, 0x1a, 0x12, 0x0a
-	.byte  0x26, 0x12, 0x0d, 0x3b, 0xd2, 0xaf, 0x80, 0xa1
-	.byte  0xae, 0x03, 0xab, 0x05, 0x53, 0x1a, 0xef, 0x90
-	.byte  0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0xad, 0x07, 0x8e
-	.byte  0x33, 0x7f, 0x20, 0x12, 0x0d, 0x51, 0x43, 0x1a
-	.byte  0x10, 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0x22
-	.byte  0xda, 0x7e, 0x10, 0x09, 0x14, 0x12, 0x0d, 0xa6
-	.byte  0x90, 0xe0, 0x00, 0xe0, 0xff, 0x20, 0xe1, 0x03
-	.byte  0x02, 0x02, 0xc8, 0xc2, 0xa8, 0xc2, 0xaa, 0x20
-	.byte  0x04, 0x03, 0x30, 0x07, 0x05, 0xd2, 0xa8, 0xd2
-	.byte  0xaa, 0x22, 0xef, 0xa2, 0xe3, 0x92, 0x1c, 0x90
-	.byte  0xf0, 0x00, 0xe0, 0xf5, 0x2c, 0x12, 0x0e, 0x2f
-	.byte  0xd2, 0xa8, 0xd2, 0xaa, 0x30, 0x1c, 0x03, 0x02
-	.byte  0x01, 0xee, 0xc2, 0x1d, 0xc2, 0x1e, 0x20, 0x17
-	.byte  0x03, 0x02, 0x01, 0xd4, 0xe5, 0x18, 0x24, 0xe1
-	.byte  0x60, 0x3b, 0x24, 0x54, 0x70, 0x03, 0x02, 0x01
-	.byte  0xd0, 0x24, 0xfa, 0x60, 0x14, 0x14, 0x60, 0x1e
-	.byte  0x14, 0x60, 0x1f, 0x14, 0x60, 0x23, 0x24, 0x74
-	.byte  0x70, 0x6c, 0xaf, 0x2c, 0x12, 0x05, 0xfb, 0x80
-	.byte  0x67, 0xe5, 0x2c, 0x30, 0xe1, 0x04, 0xd2, 0x90
-	.byte  0x80, 0x5e, 0xc2, 0x90, 0x80, 0x5a, 0xc2, 0x1f
-	.byte  0x80, 0x02, 0xd2, 0x1f, 0x85, 0x2c, 0x2f, 0x80
-	.byte  0x46, 0xd2, 0x1e, 0x80, 0x4b, 0xe5, 0x2c, 0x70
-	.byte  0x1a, 0x12, 0x0c, 0xed, 0x12, 0x08, 0xf2, 0x85
-	.byte  0x38, 0x12, 0x85, 0x39, 0x13, 0x85, 0x3a, 0x14
-	.byte  0x85, 0x09, 0x15, 0x85, 0x0a, 0x16, 0x85, 0x0b
-	.byte  0x17, 0x80, 0x2d, 0xe5, 0x2c, 0xc3, 0x94, 0x01
-	.byte  0x40, 0x13, 0xe5, 0x2c, 0xd3, 0x94, 0x06, 0x50
-	.byte  0x0c, 0xc2, 0x1f, 0x74, 0x11, 0x25, 0x2c, 0xf8
-	.byte  0xe6, 0xf5, 0x2f, 0x80, 0x0a, 0xe5, 0x2c, 0xb4
-	.byte  0x07, 0x0e, 0xc2, 0x1f, 0x85, 0x3b, 0x2f, 0xd2
-	.byte  0x20, 0x12, 0x0d, 0xb8, 0x80, 0x02, 0xd2, 0x1d
-	.byte  0xc2, 0x17, 0x80, 0x02, 0xd2, 0x1d, 0x30, 0x1d
-	.byte  0x07, 0xaf, 0x2c, 0x12, 0x05, 0x2f, 0x80, 0x08
-	.byte  0x30, 0x1e, 0x05, 0xaf, 0x2c, 0x12, 0x05, 0x97
-	.byte  0x12, 0x0e, 0x85, 0x02, 0x02, 0xc2, 0xc2, 0x1d
-	.byte  0xe5, 0x2c, 0x12, 0x0b, 0x21, 0x02, 0xb7, 0x1f
-	.byte  0x02, 0x35, 0x20, 0x02, 0xb7, 0x60, 0x02, 0x56
-	.byte  0xa7, 0x02, 0x5d, 0xa8, 0x02, 0x64, 0xa9, 0x02
-	.byte  0x48, 0xaa, 0x02, 0x64, 0xab, 0x02, 0x6d, 0xad
-	.byte  0x02, 0x74, 0xae, 0x02, 0x41, 0xc0, 0x02, 0xb7
-	.byte  0xcb, 0x02, 0x7b, 0xd0, 0x02, 0xb7, 0xd1, 0x02
-	.byte  0xb7, 0xd2, 0x02, 0xb7, 0xd3, 0x02, 0xb7, 0xd4
-	.byte  0x02, 0x98, 0xdd, 0x02, 0x8d, 0xdf, 0x02, 0xa8
-	.byte  0xfe, 0x00, 0x00, 0x02, 0xb5, 0x12, 0x0a, 0x83
-	.byte  0x8f, 0x2d, 0xc2, 0x1f, 0x85, 0x2d, 0x2f, 0x80
-	.byte  0x28, 0xc2, 0x1f, 0x75, 0x2f, 0xff, 0x80, 0x21
-	.byte  0x7f, 0x30, 0x12, 0x05, 0xfb, 0xc2, 0x1f, 0x75
-	.byte  0x2f, 0x55, 0xc2, 0x20, 0x80, 0x4b, 0x12, 0x0e
-	.byte  0x8d, 0xd2, 0x1d, 0x80, 0x5a, 0x12, 0x0e, 0xe6
-	.byte  0xd2, 0x1d, 0x80, 0x53, 0xc2, 0x1f, 0xe4, 0xf5
-	.byte  0x2f, 0xd2, 0x20, 0x80, 0x34, 0x12, 0x0e, 0x94
-	.byte  0xd2, 0x1d, 0x80, 0x43, 0x12, 0x0e, 0xf0, 0xd2
-	.byte  0x1d, 0x80, 0x3c, 0x75, 0x2e, 0x01, 0x30, 0x90
-	.byte  0x03, 0x43, 0x2e, 0x02, 0xc2, 0x1f, 0x85, 0x2e
-	.byte  0x2f, 0xd2, 0x20, 0x80, 0x14, 0xd2, 0x90, 0xc2
-	.byte  0x1f, 0x85, 0x0f, 0x2f, 0xd2, 0x20, 0x80, 0x09
-	.byte  0xc2, 0x90, 0xc2, 0x1f, 0x85, 0x0f, 0x2f, 0xd2
-	.byte  0x20, 0x12, 0x0d, 0xb8, 0xd2, 0x1d, 0x80, 0x0f
-	.byte  0xc2, 0x91, 0x7f, 0x05, 0x12, 0x00, 0x06, 0xd2
-	.byte  0x91, 0xd2, 0x1d, 0x80, 0x02, 0xd2, 0x1d, 0x30
-	.byte  0x1d, 0x03, 0x12, 0x0e, 0x85, 0xd2, 0x17, 0x85
-	.byte  0x2c, 0x18, 0x20, 0x01, 0x03, 0x12, 0x0d, 0xda
-	.byte  0x22, 0x44, 0x4d, 0x26, 0x50, 0x00, 0xff, 0x43
-	.byte  0x41, 0x3f, 0x3d, 0x3b, 0x3c, 0x58, 0x64, 0x44
-	.byte  0x42, 0x40, 0x3e, 0x0f, 0x29, 0x59, 0x65, 0x38
-	.byte  0x2a, 0x70, 0x1d, 0x10, 0x02, 0x5a, 0x66, 0x71
-	.byte  0x2c, 0x1f, 0x1e, 0x11, 0x03, 0x5b, 0x67, 0x2e
-	.byte  0x2d, 0x20, 0x12, 0x05, 0x04, 0x5c, 0x68, 0x39
-	.byte  0x2f, 0x21, 0x14, 0x13, 0x06, 0x5d, 0x69, 0x31
-	.byte  0x30, 0x23, 0x22, 0x15, 0x07, 0x5e, 0x6a, 0x72
-	.byte  0x32, 0x24, 0x16, 0x08, 0x09, 0x5f, 0x6b, 0x33
-	.byte  0x25, 0x17, 0x18, 0x0b, 0x0a, 0x60, 0x6c, 0x34
-	.byte  0x35, 0x26, 0x27, 0x19, 0x0c, 0x61, 0x6d, 0x73
-	.byte  0x28, 0x74, 0x1a, 0x0d, 0x62, 0x6e, 0x3a, 0x36
-	.byte  0x1c, 0x1b, 0x75, 0x2b, 0x63, 0x76, 0x55, 0x56
-	.byte  0x77, 0x78, 0x79, 0x7a, 0x0e, 0x7b, 0x7c, 0x4f
-	.byte  0x7d, 0x4b, 0x47, 0x7e, 0x7f, 0x6f, 0x52, 0x53
-	.byte  0x50, 0x4c, 0x4d, 0x48, 0x01, 0x45, 0x57, 0x4e
-	.byte  0x51, 0x4a, 0x37, 0x49, 0x46, 0x54, 0x00, 0x00
-	.byte  0x00, 0x41, 0x54, 0x00, 0x01, 0x01, 0x02, 0x01
-	.byte  0x02, 0x02, 0x03, 0x01, 0x02, 0x02, 0x03, 0x02
-	.byte  0x03, 0x03, 0x04, 0x14, 0x23, 0x14, 0x3a, 0x14
-	.byte  0x4d, 0x42, 0x32, 0x23, 0x20, 0x0c, 0x03, 0x02
-	.byte  0x04, 0x08, 0xc2, 0x1a, 0xc2, 0x1b, 0xe5, 0x10
-	.byte  0x30, 0xe7, 0x57, 0xe5, 0x11, 0xae, 0x10, 0x78
-	.byte  0x06, 0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9
-	.byte  0xf5, 0x26, 0xff, 0x12, 0x0d, 0xca, 0x8f, 0x27
-	.byte  0xe5, 0x10, 0xc4, 0x13, 0x13, 0x54, 0x03, 0xff
-	.byte  0xe5, 0x27, 0x54, 0x01, 0xb5, 0x07, 0x05, 0xe4
-	.byte  0x7f, 0x01, 0x80, 0x02, 0x7f, 0x00, 0xef, 0x30
-	.byte  0xe0, 0x04, 0xd2, 0x1b, 0x80, 0x24, 0x20, 0x13
-	.byte  0x1f, 0xaf, 0x26, 0x12, 0x07, 0x79, 0xaf, 0x26
-	.byte  0x12, 0x09, 0xf6, 0x8e, 0x28, 0x8f, 0x29, 0xe5
-	.byte  0x29, 0xf4, 0x70, 0x03, 0xe5, 0x28, 0xf4, 0x60
-	.byte  0x09, 0x85, 0x29, 0x26, 0xd2, 0x1a, 0x80, 0x02
-	.byte  0xd2, 0x1a, 0x30, 0x1a, 0x1b, 0xc2, 0x27, 0x7f
-	.byte  0x07, 0x12, 0x0b, 0x6c, 0xc2, 0x27, 0x7f, 0x06
-	.byte  0x12, 0x0b, 0x6c, 0xa2, 0x13, 0x92, 0x25, 0x85
-	.byte  0x26, 0x31, 0x12, 0x08, 0xbb, 0xc2, 0x0c, 0x22
-	.byte  0x30, 0x1b, 0x10, 0xa2, 0x13, 0x92, 0x21, 0x75
-	.byte  0x30, 0xff, 0xd2, 0x22, 0xc2, 0x23, 0xd2, 0x24
-	.byte  0x02, 0x06, 0xee, 0xc2, 0x0c, 0x12, 0x0e, 0x7d
-	.byte  0x22, 0xe4, 0xf5, 0x26, 0xf5, 0x27, 0x75, 0x28
-	.byte  0x0f, 0x75, 0x29, 0xff, 0xe5, 0x27, 0x25, 0x29
-	.byte  0xff, 0xe5, 0x26, 0x35, 0x28, 0xc3, 0x13, 0xf5
-	.byte  0x2a, 0xef, 0x13, 0xf5, 0x2b, 0xff, 0xae, 0x2a
-	.byte  0x12, 0x0e, 0x15, 0xbf, 0xff, 0x0e, 0xe5, 0x2b
-	.byte  0x24, 0xff, 0xf5, 0x29, 0xe5, 0x2a, 0x34, 0xff
-	.byte  0xf5, 0x28, 0x80, 0x47, 0xef, 0x70, 0x0d, 0xe5
-	.byte  0x2b, 0x24, 0x01, 0xf5, 0x27, 0xe4, 0x35, 0x2a
-	.byte  0xf5, 0x26, 0x80, 0x37, 0x75, 0x2c, 0xff, 0xe4
-	.byte  0xf5, 0x2d, 0xe5, 0x2c, 0xc3, 0x13, 0xf5, 0x2c
-	.byte  0xb5, 0x07, 0x1c, 0xe5, 0x2b, 0xae, 0x2a, 0x78
-	.byte  0x03, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8, 0xf9
-	.byte  0x7c, 0x00, 0x25, 0x2d, 0xff, 0xec, 0x3e, 0xcf
-	.byte  0x24, 0x01, 0xcf, 0x34, 0x00, 0xfe, 0x22, 0x05
-	.byte  0x2d, 0xe5, 0x2d, 0xb4, 0x07, 0xd4, 0x7e, 0xff
-	.byte  0x7f, 0xff, 0x22, 0xd3, 0xe5, 0x27, 0x95, 0x29
-	.byte  0xe5, 0x28, 0x64, 0x80, 0xf8, 0xe5, 0x26, 0x64
-	.byte  0x80, 0x98, 0x40, 0x80, 0xe5, 0x27, 0xae, 0x26
-	.byte  0x78, 0x03, 0xc3, 0x33, 0xce, 0x33, 0xce, 0xd8
-	.byte  0xf9, 0xff, 0x22, 0x78, 0x7f, 0xe4, 0xf6, 0xd8
-	.byte  0xfd, 0x75, 0x81, 0x3b, 0x02, 0x04, 0xea, 0x02
-	.byte  0x00, 0x16, 0xe4, 0x93, 0xa3, 0xf8, 0xe4, 0x93
-	.byte  0xa3, 0x40, 0x03, 0xf6, 0x80, 0x01, 0xf2, 0x08
-	.byte  0xdf, 0xf4, 0x80, 0x29, 0xe4, 0x93, 0xa3, 0xf8
-	.byte  0x54, 0x07, 0x24, 0x0c, 0xc8, 0xc3, 0x33, 0xc4
-	.byte  0x54, 0x0f, 0x44, 0x20, 0xc8, 0x83, 0x40, 0x04
-	.byte  0xf4, 0x56, 0x80, 0x01, 0x46, 0xf6, 0xdf, 0xe4
-	.byte  0x80, 0x0b, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20
-	.byte  0x40, 0x80, 0x90, 0x08, 0x80, 0xe4, 0x7e, 0x01
-	.byte  0x93, 0x60, 0xbc, 0xa3, 0xff, 0x54, 0x3f, 0x30
-	.byte  0xe5, 0x09, 0x54, 0x1f, 0xfe, 0xe4, 0x93, 0xa3
-	.byte  0x60, 0x01, 0x0e, 0xcf, 0x54, 0xc0, 0x25, 0xe0
-	.byte  0x60, 0xa8, 0x40, 0xb8, 0xe4, 0x93, 0xa3, 0xfa
-	.byte  0xe4, 0x93, 0xa3, 0xf8, 0xe4, 0x93, 0xa3, 0xc8
-	.byte  0xc5, 0x82, 0xc8, 0xca, 0xc5, 0x83, 0xca, 0xf0
-	.byte  0xa3, 0xc8, 0xc5, 0x82, 0xc8, 0xca, 0xc5, 0x83
-	.byte  0xca, 0xdf, 0xe9, 0xde, 0xe7, 0x80, 0xbe, 0xd2
-	.byte  0x0d, 0xc2, 0x96, 0xd2, 0x0e, 0xd2, 0x10, 0xc2
-	.byte  0x94, 0x8f, 0x08, 0x12, 0x0d, 0xca, 0xef, 0x13
-	.byte  0xb3, 0x92, 0x14, 0xd2, 0x16, 0xe4, 0xf5, 0x0c
-	.byte  0x7f, 0x28, 0x12, 0x00, 0x06, 0xc2, 0x97, 0xd2
-	.byte  0x03, 0xc2, 0x0a, 0x7f, 0xe8, 0x7e, 0xfd, 0x12
-	.byte  0x0c, 0x79, 0xc2, 0x0d, 0xd2, 0x96, 0x30, 0x16
-	.byte  0x16, 0x12, 0x0e, 0x62, 0x50, 0xf8, 0xc2, 0xaf
-	.byte  0xd2, 0x97, 0xc2, 0x21, 0x12, 0x06, 0xe5, 0xc2
-	.byte  0x16, 0xe4, 0xf5, 0x0c, 0xd2, 0xaf, 0x22, 0x7f
-	.byte  0xe8, 0x7e, 0xfd, 0x12, 0x0c, 0x79, 0x20, 0x04
-	.byte  0x12, 0x20, 0x0a, 0x0f, 0x12, 0x0e, 0x62, 0x50
-	.byte  0xf5, 0xc2, 0xaf, 0xc2, 0x21, 0x12, 0x06, 0xe5
-	.byte  0xd2, 0xaf, 0x22, 0x12, 0x07, 0x2e, 0x22, 0xd2
-	.byte  0x10, 0xc2, 0x94, 0xd2, 0x0a, 0xd2, 0x0d, 0xc2
-	.byte  0x96, 0x8f, 0x08, 0x12, 0x0d, 0xca, 0xef, 0x13
-	.byte  0xb3, 0x92, 0x14, 0xd2, 0x16, 0xe4, 0xf5, 0x0e
-	.byte  0x7f, 0x28, 0x12, 0x00, 0x06, 0xc2, 0x95, 0xd2
-	.byte  0x05, 0xc2, 0x0e, 0x7f, 0xe8, 0x7e, 0xfd, 0x12
-	.byte  0x0c, 0x79, 0xc2, 0x10, 0xd2, 0x94, 0x30, 0x16
-	.byte  0x14, 0x12, 0x0e, 0x62, 0x50, 0xf8, 0xc2, 0xaf
-	.byte  0xd2, 0x95, 0x12, 0x06, 0xe3, 0xc2, 0x16, 0xe4
-	.byte  0xf5, 0x0e, 0xd2, 0xaf, 0x22, 0x7f, 0xe8, 0x7e
-	.byte  0xfd, 0x12, 0x0c, 0x79, 0x20, 0x07, 0x10, 0x20
-	.byte  0x0e, 0x0d, 0x12, 0x0e, 0x62, 0x50, 0xf5, 0xc2
-	.byte  0xaf, 0x12, 0x06, 0xe3, 0xd2, 0xaf, 0x22, 0x12
-	.byte  0x07, 0x2e, 0x22, 0xad, 0x07, 0xed, 0x30, 0xe6
-	.byte  0x04, 0xd2, 0x0f, 0x80, 0x02, 0xc2, 0x0f, 0xed
-	.byte  0x30, 0xe5, 0x05, 0x12, 0x0e, 0x8d, 0x80, 0x03
-	.byte  0x12, 0x0e, 0xe6, 0xed, 0x30, 0xe4, 0x05, 0x12
-	.byte  0x0e, 0x94, 0x80, 0x03, 0x12, 0x0e, 0xf0, 0xed
-	.byte  0x30, 0xe2, 0x04, 0xd2, 0x27, 0x80, 0x02, 0xc2
-	.byte  0x27, 0x7f, 0x02, 0x12, 0x0b, 0x6c, 0xed, 0x30
-	.byte  0xe1, 0x05, 0x12, 0x0f, 0x14, 0x80, 0x03, 0x12
-	.byte  0x0f, 0x11, 0xed, 0x30, 0xe0, 0x0b, 0x12, 0x0f
-	.byte  0x1a, 0x20, 0x11, 0x08, 0xd2, 0x11, 0xd2, 0x01
-	.byte  0x22, 0x12, 0x0f, 0x17, 0x22, 0x7f, 0x02, 0x12
-	.byte  0x00, 0x06, 0x20, 0x94, 0x42, 0xa2, 0x95, 0x92
-	.byte  0x18, 0x05, 0x0e, 0xe5, 0x0e, 0xb4, 0x01, 0x12
-	.byte  0x20, 0x18, 0x0a, 0xd2, 0x07, 0xd2, 0x0a, 0xd2
-	.byte  0x0d, 0xc2, 0x96, 0x80, 0x19, 0xe4, 0xf5, 0x0e
-	.byte  0x80, 0x14, 0xe5, 0x0e, 0xb4, 0x0b, 0x0f, 0xd2
-	.byte  0x0e, 0xd2, 0x10, 0xc2, 0x94, 0xd2, 0x13, 0xd2
-	.byte  0x0c, 0xe4, 0xf5, 0x0e, 0xc2, 0x07, 0xe5, 0x10
-	.byte  0xc3, 0x13, 0xf5, 0x10, 0xe5, 0x11, 0x13, 0xf5
-	.byte  0x11, 0x30, 0x18, 0x03, 0x43, 0x10, 0x80, 0x22
-	.byte  0x7f, 0x02, 0x12, 0x00, 0x06, 0x20, 0x96, 0x42
-	.byte  0xa2, 0x97, 0x92, 0x19, 0x05, 0x0c, 0xe5, 0x0c
-	.byte  0xb4, 0x01, 0x12, 0x20, 0x19, 0x0a, 0xd2, 0x04
-	.byte  0xd2, 0x0e, 0xd2, 0x10, 0xc2, 0x94, 0x80, 0x19
-	.byte  0xe4, 0xf5, 0x0c, 0x80, 0x14, 0xe5, 0x0c, 0xb4
-	.byte  0x0b, 0x0f, 0xd2, 0x0a, 0xd2, 0x0d, 0xc2, 0x96
-	.byte  0xc2, 0x13, 0xd2, 0x0c, 0xe4, 0xf5, 0x0c, 0xc2
-	.byte  0x04, 0xe5, 0x10, 0xc3, 0x13, 0xf5, 0x10, 0xe5
-	.byte  0x11, 0x13, 0xf5, 0x11, 0x30, 0x19, 0x03, 0x43
-	.byte  0x10, 0x80, 0x22, 0xd2, 0x21, 0x75, 0x30, 0xfe
-	.byte  0xd2, 0x22, 0xd2, 0x23, 0xc2, 0x24, 0xd2, 0x0a
-	.byte  0xd2, 0x0d, 0xc2, 0x96, 0xd2, 0x0e, 0xd2, 0x10
-	.byte  0xc2, 0x94, 0xa2, 0x23, 0x92, 0x27, 0x7f, 0x06
-	.byte  0x12, 0x0b, 0x6c, 0xa2, 0x24, 0x92, 0x27, 0x7f
-	.byte  0x07, 0x12, 0x0b, 0x6c, 0x30, 0x22, 0x0c, 0xa2
-	.byte  0x21, 0x92, 0x25, 0x85, 0x30, 0x31, 0x12, 0x08
-	.byte  0xbb, 0x80, 0x10, 0xa2, 0x21, 0x92, 0x26, 0x85
-	.byte  0x30, 0x32, 0x12, 0x0b, 0xf9, 0xc2, 0x92, 0xc2
-	.byte  0x93, 0xd2, 0x09, 0xc2, 0x0c, 0x22, 0x20, 0x04
-	.byte  0x03, 0x30, 0x07, 0x44, 0x7f, 0xe8, 0x7e, 0xfd
-	.byte  0x12, 0x0c, 0x79, 0x20, 0x04, 0x03, 0x30, 0x07
-	.byte  0x37, 0x12, 0x0e, 0x62, 0x50, 0xf5, 0xc2, 0xaf
-	.byte  0x20, 0x04, 0x03, 0x30, 0x07, 0x26, 0x30, 0x04
-	.byte  0x04, 0xc2, 0x1f, 0x80, 0x02, 0xd2, 0x1f, 0xe4
-	.byte  0xf5, 0x0c, 0xc2, 0x04, 0xf5, 0x0e, 0xc2, 0x07
-	.byte  0x12, 0x0e, 0xeb, 0x12, 0x0e, 0x80, 0xd2, 0xaf
-	.byte  0xa2, 0x1f, 0x92, 0x21, 0x75, 0x30, 0xff, 0x12
-	.byte  0x06, 0xe8, 0x80, 0xc7, 0xd2, 0xaf, 0x80, 0xc3
-	.byte  0x22, 0xe5, 0x19, 0x60, 0x03, 0xb4, 0x02, 0x09
-	.byte  0xe5, 0x0d, 0x90, 0x03, 0x63, 0x93, 0x6f, 0x60
-	.byte  0x0b, 0xe5, 0x19, 0x64, 0x01, 0x70, 0x2d, 0xef
-	.byte  0x64, 0xf0, 0x70, 0x28, 0x05, 0x19, 0xe5, 0x19
-	.byte  0xd3, 0x94, 0x02, 0x40, 0x24, 0xe4, 0xf5, 0x19
-	.byte  0x05, 0x0d, 0xe5, 0x0d, 0x94, 0x09, 0x40, 0x19
-	.byte  0x75, 0x2a, 0x05, 0xe4, 0xff, 0x12, 0x0c, 0x3b
-	.byte  0x7f, 0x07, 0x12, 0x0c, 0x3b, 0xd5, 0x2a, 0xf3
-	.byte  0xe4, 0xf5, 0x0d, 0x22, 0xe4, 0xf5, 0x0d, 0xf5
-	.byte  0x19, 0x22, 0xe5, 0x3b, 0x64, 0x15, 0x70, 0x41
-	.byte  0x12, 0x0c, 0xed, 0xe5, 0x3a, 0x30, 0xe0, 0x05
-	.byte  0x75, 0x26, 0x80, 0x80, 0x03, 0xe4, 0xf5, 0x26
-	.byte  0xe5, 0x3a, 0xc3, 0x13, 0xf5, 0x3a, 0xe5, 0x39
-	.byte  0x30, 0xe0, 0x03, 0x43, 0x3a, 0x80, 0xe5, 0x39
-	.byte  0xc3, 0x13, 0xf5, 0x39, 0xe5, 0x38, 0x30, 0xe0
-	.byte  0x03, 0x43, 0x39, 0x80, 0xc2, 0xb6, 0x90, 0xd0
-	.byte  0x01, 0xe4, 0xf0, 0xa3, 0xe5, 0x26, 0xf0, 0xa3
-	.byte  0xe5, 0x3a, 0xf0, 0xa3, 0xe5, 0x39, 0xf0, 0xd2
-	.byte  0xb6, 0x22, 0x20, 0x94, 0x37, 0x05, 0x0e, 0xe5
-	.byte  0x0e, 0xd3, 0x94, 0x08, 0x50, 0x12, 0xe5, 0x08
-	.byte  0x30, 0xe0, 0x04, 0xd2, 0x95, 0x80, 0x02, 0xc2
-	.byte  0x95, 0xe5, 0x08, 0xc3, 0x13, 0xf5, 0x08, 0x22
-	.byte  0xe5, 0x0e, 0xb4, 0x09, 0x05, 0xa2, 0x14, 0x92
-	.byte  0x95, 0x22, 0xe5, 0x0e, 0xb4, 0x0a, 0x03, 0xd2
-	.byte  0x95, 0x22, 0xe5, 0x0e, 0xb4, 0x0b, 0x05, 0xc2
-	.byte  0x16, 0xe4, 0xf5, 0x0e, 0x22, 0x20, 0x96, 0x37
-	.byte  0x05, 0x0c, 0xe5, 0x0c, 0xd3, 0x94, 0x08, 0x50
-	.byte  0x12, 0xe5, 0x08, 0x30, 0xe0, 0x04, 0xd2, 0x97
-	.byte  0x80, 0x02, 0xc2, 0x97, 0xe5, 0x08, 0xc3, 0x13
-	.byte  0xf5, 0x08, 0x22, 0xe5, 0x0c, 0xb4, 0x09, 0x05
-	.byte  0xa2, 0x14, 0x92, 0x97, 0x22, 0xe5, 0x0c, 0xb4
-	.byte  0x0a, 0x03, 0xd2, 0x97, 0x22, 0xe5, 0x0c, 0xb4
-	.byte  0x0b, 0x05, 0xc2, 0x16, 0xe4, 0xf5, 0x0c, 0x22
-	.byte  0x01, 0x0c, 0x00, 0xc1, 0x04, 0xc1, 0x0a, 0xc1
-	.byte  0x83, 0xc1, 0x0c, 0xc1, 0x09, 0xc1, 0x02, 0xc1
-	.byte  0x16, 0xc1, 0x08, 0x01, 0x0e, 0x00, 0xc1, 0x07
-	.byte  0xc1, 0x0e, 0xc1, 0x85, 0xc1, 0x8b, 0xc1, 0x86
-	.byte  0xc1, 0x8f, 0xc1, 0x12, 0xc1, 0x00, 0xc1, 0x11
-	.byte  0xc1, 0x01, 0xc1, 0x17, 0x01, 0x0d, 0x00, 0x01
-	.byte  0x19, 0x00, 0x01, 0x1a, 0x00, 0x01, 0x34, 0x03
-	.byte  0xc1, 0x29, 0x00, 0xa2, 0x25, 0x92, 0x26, 0x85
-	.byte  0x31, 0x32, 0x12, 0x0b, 0xf9, 0xc2, 0x92, 0xc2
-	.byte  0x93, 0x20, 0x25, 0x03, 0x20, 0x06, 0x06, 0x30
-	.byte  0x25, 0x1d, 0x30, 0x0b, 0x1a, 0x7f, 0x69, 0x7e
-	.byte  0x00, 0x12, 0x0c, 0x79, 0x12, 0x0e, 0x62, 0x50
-	.byte  0xfb, 0x12, 0x0e, 0xb0, 0x50, 0x09, 0x20, 0x25
-	.byte  0x04, 0xd2, 0x92, 0x80, 0x02, 0xd2, 0x93, 0xd2
-	.byte  0x09, 0x22, 0x90, 0x0f, 0xfc, 0xe4, 0x93, 0xfe
-	.byte  0x74, 0x01, 0x93, 0xff, 0xc3, 0x95, 0x3a, 0xf5
-	.byte  0x0b, 0xee, 0x95, 0x39, 0xf5, 0x0a, 0x90, 0x0f
-	.byte  0xfb, 0xe4, 0x93, 0xc3, 0x95, 0x38, 0xf5, 0x09
-	.byte  0xc3, 0xef, 0x95, 0x3a, 0xee, 0x95, 0x39, 0x50
-	.byte  0x02, 0x15, 0x09, 0xe5, 0x09, 0x30, 0xe7, 0x07
-	.byte  0xe4, 0xf5, 0x09, 0xf5, 0x0a, 0xf5, 0x0b, 0x22
-	.byte  0x05, 0x35, 0xaf, 0x35, 0xae, 0x07, 0xee, 0x14
-	.byte  0x13, 0x13, 0x13, 0x54, 0x1f, 0xfd, 0xee, 0x54
-	.byte  0x07, 0xff, 0x70, 0x06, 0xf5, 0x26, 0xf5, 0x27
-	.byte  0x80, 0x15, 0x74, 0xff, 0x7e, 0x00, 0xa8, 0x07
-	.byte  0x08, 0x80, 0x06, 0xce, 0xa2, 0xe7, 0x13, 0xce
-	.byte  0x13, 0xd8, 0xf8, 0xf5, 0x27, 0x8e, 0x26, 0xaf
-	.byte  0x05, 0xad, 0x27, 0x02, 0x0c, 0x5a, 0xe4, 0xff
-	.byte  0x7e, 0x01, 0xef, 0xc3, 0x94, 0x08, 0x50, 0x27
-	.byte  0xef, 0x60, 0x1d, 0x64, 0x01, 0x60, 0x19, 0xef
-	.byte  0x64, 0x03, 0x60, 0x14, 0xee, 0x44, 0x02, 0x54
-	.byte  0xfe, 0x90, 0xe0, 0x00, 0xf0, 0x54, 0xf4, 0xfd
-	.byte  0xee, 0x54, 0xf4, 0x6d, 0x60, 0x02, 0xd3, 0x22
-	.byte  0x0f, 0xee, 0x25, 0xe0, 0xfe, 0x80, 0xd3, 0xc3
-	.byte  0x22, 0xad, 0x07, 0xac, 0x06, 0xed, 0x24, 0xff
-	.byte  0xff, 0xec, 0x34, 0xff, 0xfe, 0xef, 0x78, 0x03
-	.byte  0xce, 0xc3, 0x13, 0xce, 0x13, 0xd8, 0xf9, 0xff
-	.byte  0xed, 0x54, 0x07, 0xfd, 0x70, 0x04, 0xf5, 0x26
-	.byte  0x80, 0x0d, 0x74, 0xff, 0xa8, 0x05, 0x08, 0x80
-	.byte  0x02, 0xc3, 0x13, 0xd8, 0xfc, 0xf5, 0x26, 0xad
-	.byte  0x26, 0x02, 0x0a, 0xad, 0xc2, 0x28, 0x20, 0x29
-	.byte  0x0f, 0x12, 0x0f, 0x0d, 0x8f, 0x3b, 0xe5, 0x3b
-	.byte  0xb4, 0x15, 0x03, 0x75, 0x34, 0x1f, 0xd2, 0x29
-	.byte  0x12, 0x0a, 0x56, 0x8f, 0x35, 0xe5, 0x35, 0x30
-	.byte  0xe0, 0x0c, 0x12, 0x0d, 0x7d, 0x12, 0x09, 0x28
-	.byte  0xe4, 0xf5, 0x36, 0xf5, 0x37, 0x22, 0x12, 0x04
-	.byte  0x09, 0x8e, 0x36, 0x8f, 0x37, 0x22, 0x20, 0x0f
-	.byte  0x03, 0x7e, 0x00, 0x22, 0xbf, 0xf0, 0x07, 0xd2
-	.byte  0x15, 0x7e, 0xff, 0x7f, 0xff, 0x22, 0xef, 0xc3
-	.byte  0x94, 0x85, 0x40, 0x03, 0x7e, 0x00, 0x22, 0xef
-	.byte  0x90, 0x02, 0xce, 0x93, 0xfe, 0x70, 0x02, 0xfe
-	.byte  0x22, 0x30, 0x15, 0x03, 0x43, 0x06, 0x80, 0xc2
-	.byte  0x15, 0xaf, 0x06, 0x7e, 0x00, 0x22, 0xa2, 0x1a
-	.byte  0x92, 0x28, 0x05, 0x37, 0xe5, 0x37, 0x70, 0x02
-	.byte  0x05, 0x36, 0xc3, 0xe5, 0x36, 0x94, 0x80, 0x50
-	.byte  0x07, 0xaf, 0x37, 0xae, 0x36, 0x02, 0x09, 0x91
-	.byte  0xe5, 0x35, 0xc3, 0x94, 0x10, 0x50, 0x0e, 0x12
-	.byte  0x09, 0x28, 0x12, 0x0d, 0x7d, 0x12, 0x09, 0x28
-	.byte  0xe4, 0xf5, 0x36, 0xf5, 0x37, 0x22, 0xe4, 0xff
-	.byte  0x12, 0x0e, 0x23, 0x7e, 0xff, 0xe4, 0xf5, 0x26
-	.byte  0xe5, 0x26, 0xb4, 0x08, 0x07, 0x7f, 0x01, 0x12
-	.byte  0x0e, 0x23, 0x7e, 0xff, 0xee, 0xb5, 0x07, 0x03
-	.byte  0xaf, 0x26, 0x22, 0xee, 0xc3, 0x13, 0xfe, 0x05
-	.byte  0x26, 0xe5, 0x26, 0xd3, 0x94, 0x10, 0x40, 0xe0
-	.byte  0x7f, 0xff, 0x22, 0xe4, 0xff, 0x30, 0x0f, 0x02
-	.byte  0x7f, 0x40, 0x20, 0x05, 0x03, 0x43, 0x07, 0x20
-	.byte  0x20, 0x03, 0x03, 0x43, 0x07, 0x10, 0x90, 0xe0
-	.byte  0x00, 0xe0, 0x30, 0xe2, 0x03, 0x43, 0x07, 0x04
-	.byte  0x30, 0x0b, 0x03, 0x43, 0x07, 0x02, 0x30, 0x06
-	.byte  0x03, 0x43, 0x07, 0x01, 0x22, 0x8e, 0x27, 0x8f
-	.byte  0x28, 0x8d, 0x29, 0x12, 0x0e, 0x74, 0xe5, 0x27
-	.byte  0x24, 0xd0, 0xf5, 0x2a, 0xe5, 0x28, 0xf5, 0x2b
-	.byte  0x12, 0x0e, 0xa2, 0x85, 0x29, 0x2f, 0xab, 0x2b
-	.byte  0xad, 0x2a, 0xaf, 0x34, 0x12, 0x0b, 0x47, 0x12
-	.byte  0x0e, 0xa9, 0x02, 0x0d, 0xea, 0xc0, 0xe0, 0xc0
-	.byte  0xf0, 0xc0, 0xd0, 0x75, 0xd0, 0x00, 0xc0, 0x06
-	.byte  0xc0, 0x07, 0x20, 0x10, 0x0b, 0x30, 0x16, 0x05
-	.byte  0x12, 0x08, 0x0a, 0x80, 0x03, 0x12, 0x06, 0x4d
-	.byte  0xd0, 0x07, 0xd0, 0x06, 0xd0, 0xd0, 0xd0, 0xf0
-	.byte  0xd0, 0xe0, 0x32, 0xc0, 0xe0, 0xc0, 0xf0, 0xc0
-	.byte  0xd0, 0x75, 0xd0, 0x00, 0xc0, 0x06, 0xc0, 0x07
-	.byte  0x20, 0x0d, 0x0b, 0x30, 0x16, 0x05, 0x12, 0x08
-	.byte  0x45, 0x80, 0x03, 0x12, 0x06, 0x98, 0xd0, 0x07
-	.byte  0xd0, 0x06, 0xd0, 0xd0, 0xd0, 0xf0, 0xd0, 0xe0
-	.byte  0x32, 0xd0, 0x83, 0xd0, 0x82, 0xf8, 0xe4, 0x93
-	.byte  0x70, 0x12, 0x74, 0x01, 0x93, 0x70, 0x0d, 0xa3
-	.byte  0xa3, 0x93, 0xf8, 0x74, 0x01, 0x93, 0xf5, 0x82
-	.byte  0x88, 0x83, 0xe4, 0x73, 0x74, 0x02, 0x93, 0x68
-	.byte  0x60, 0xef, 0xa3, 0xa3, 0xa3, 0x80, 0xdf, 0xae
-	.byte  0x03, 0xab, 0x05, 0x53, 0x1a, 0xef, 0x90, 0xd0
-	.byte  0x00, 0xe5, 0x1a, 0xf0, 0xad, 0x07, 0x8e, 0x33
-	.byte  0x7f, 0x02, 0x12, 0x0d, 0x51, 0xaf, 0x2f, 0x12
-	.byte  0x0c, 0xd0, 0x43, 0x1a, 0x10, 0x90, 0xd0, 0x00
-	.byte  0xe5, 0x1a, 0xf0, 0x22, 0x74, 0x01, 0xa8, 0x07
-	.byte  0x08, 0x80, 0x02, 0xc3, 0x33, 0xd8, 0xfc, 0xff
-	.byte  0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02, 0xfe, 0xef
-	.byte  0x30, 0x27, 0x04, 0x42, 0x06, 0x80, 0x03, 0xf4
-	.byte  0x52, 0x06, 0x90, 0xe0, 0x00, 0xee, 0xf0, 0x22
-	.byte  0x12, 0x0e, 0x07, 0x40, 0x05, 0x12, 0x01, 0x05
-	.byte  0x80, 0xf6, 0x12, 0x0e, 0xc8, 0x12, 0x0e, 0xd4
-	.byte  0xc2, 0x1f, 0x75, 0x2f, 0xee, 0xa2, 0x06, 0x92
-	.byte  0x20, 0x12, 0x0d, 0xb8, 0x90, 0xd0, 0x00, 0xe0
-	.byte  0x30, 0xe1, 0xf9, 0x22, 0xae, 0x03, 0xab, 0x05
-	.byte  0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00, 0xe5, 0x1a
-	.byte  0xf0, 0xad, 0x07, 0x8e, 0x33, 0x7f, 0x03, 0x12
-	.byte  0x0d, 0x51, 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10
-	.byte  0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0xe5
-	.byte  0x1a, 0x54, 0x9f, 0xfd, 0x44, 0x20, 0xfe, 0x7c
-	.byte  0x08, 0xef, 0x25, 0xe0, 0xff, 0x90, 0xd0, 0x00
-	.byte  0xed, 0xf0, 0xe0, 0x30, 0xe4, 0x03, 0x43, 0x07
-	.byte  0x01, 0x90, 0xd0, 0x00, 0xee, 0xf0, 0xdc, 0xe9
-	.byte  0x22, 0x90, 0xf0, 0x00, 0xe5, 0x32, 0xf0, 0xf5
-	.byte  0x0f, 0xa2, 0x26, 0x92, 0x27, 0x7f, 0x05, 0x12
-	.byte  0x0b, 0x6c, 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02
-	.byte  0x54, 0xfe, 0xfe, 0xf0, 0x44, 0x01, 0xf0, 0xee
-	.byte  0xf0, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00
-	.byte  0xe5, 0x1a, 0xf0, 0x7f, 0x9f, 0x12, 0x0c, 0xd0
-	.byte  0x12, 0x0b, 0xd7, 0x12, 0x0b, 0xd7, 0x12, 0x0b
-	.byte  0xd7, 0x43, 0x1a, 0x10, 0x90, 0xd0, 0x00, 0xe5
-	.byte  0x1a, 0xf0, 0x22, 0x8f, 0x2b, 0x7f, 0xed, 0x12
-	.byte  0x05, 0x2f, 0xaf, 0x2b, 0x12, 0x05, 0x2f, 0x75
-	.byte  0x2c, 0x0a, 0x7f, 0xe8, 0x7e, 0xfd, 0x12, 0x0c
-	.byte  0x79, 0x12, 0x0e, 0x62, 0x50, 0xfb, 0xd5, 0x2c
-	.byte  0xf1, 0x22, 0x8f, 0x28, 0x8d, 0x29, 0x12, 0x0e
-	.byte  0x74, 0x12, 0x0e, 0xa2, 0xe5, 0x28, 0x24, 0xfe
-	.byte  0xfb, 0x85, 0x29, 0x2f, 0x7d, 0xef, 0xaf, 0x34
-	.byte  0x12, 0x0b, 0x47, 0x12, 0x0e, 0xa9, 0x02, 0x0d
-	.byte  0xea, 0xad, 0x07, 0xac, 0x06, 0xc2, 0x8c, 0xed
-	.byte  0xf4, 0xff, 0xec, 0xf4, 0xfe, 0xef, 0x24, 0x01
-	.byte  0xfd, 0xe4, 0x3e, 0xf5, 0x8c, 0xaf, 0x05, 0x8f
-	.byte  0x8a, 0xc2, 0x8d, 0xd2, 0x8c, 0x22, 0xad, 0x07
-	.byte  0xac, 0x06, 0xc2, 0xca, 0xed, 0xf4, 0xff, 0xec
-	.byte  0xf4, 0xfe, 0xef, 0x24, 0x01, 0xfd, 0xe4, 0x3e
-	.byte  0xf5, 0xcd, 0xaf, 0x05, 0x8f, 0xcc, 0xc2, 0xcf
-	.byte  0xd2, 0xca, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0
-	.byte  0x00, 0xe5, 0x1a, 0xf0, 0x7f, 0x05, 0x12, 0x0c
-	.byte  0xd0, 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10, 0x90
-	.byte  0xd0, 0x00, 0xe5, 0x1a, 0xf0, 0xef, 0x13, 0x22
-	.byte  0xe5, 0x1a, 0x54, 0x9f, 0xfe, 0x44, 0x40, 0xfd
-	.byte  0x7c, 0x08, 0x90, 0xd0, 0x00, 0xef, 0x33, 0xff
-	.byte  0x50, 0x03, 0xed, 0x80, 0x01, 0xee, 0xf0, 0x44
-	.byte  0x20, 0xf0, 0xdc, 0xf1, 0x22, 0x12, 0x0f, 0x04
-	.byte  0x8e, 0x39, 0x8f, 0x3a, 0x12, 0x0f, 0x1d, 0x8f
-	.byte  0x38, 0xe5, 0x38, 0x30, 0xe1, 0x03, 0x43, 0x39
-	.byte  0x80, 0xe5, 0x38, 0x13, 0x13, 0x54, 0x3f, 0xf5
-	.byte  0x38, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00
-	.byte  0xe5, 0x1a, 0xf0, 0x7f, 0x05, 0x12, 0x0c, 0xd0
-	.byte  0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10, 0x90, 0xd0
-	.byte  0x00, 0xe5, 0x1a, 0xf0, 0x22, 0x12, 0x0e, 0xc8
-	.byte  0x12, 0x0e, 0xd4, 0x90, 0xd0, 0x00, 0xe0, 0x20
-	.byte  0xe1, 0x08, 0x12, 0x03, 0x6c, 0x12, 0x01, 0x05
-	.byte  0x80, 0xf1, 0x22, 0x12, 0x0c, 0xed, 0x12, 0x08
-	.byte  0xf2, 0xe5, 0x09, 0x70, 0x0b, 0xe5, 0x0a, 0x70
-	.byte  0x07, 0xe5, 0x0b, 0x70, 0x03, 0x12, 0x0e, 0xda
-	.byte  0x22, 0x8d, 0x31, 0x8b, 0x32, 0x12, 0x0c, 0xd0
-	.byte  0xaf, 0x31, 0x12, 0x0c, 0xd0, 0xaf, 0x32, 0x12
-	.byte  0x0c, 0xd0, 0xaf, 0x33, 0x02, 0x0c, 0xd0, 0x53
-	.byte  0x1a, 0xef, 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0
-	.byte  0x12, 0x0c, 0xd0, 0x43, 0x1a, 0x10, 0x90, 0xd0
-	.byte  0x00, 0xe5, 0x1a, 0xf0, 0x22, 0x12, 0x0e, 0x74
-	.byte  0x12, 0x0e, 0xa2, 0xe4, 0xfb, 0x7d, 0xd0, 0xaf
-	.byte  0x34, 0x12, 0x00, 0xe0, 0x12, 0x0e, 0xa9, 0x02
-	.byte  0x0d, 0xea, 0x53, 0x1a, 0xfb, 0x90, 0xd0, 0x00
-	.byte  0xe5, 0x1a, 0xf0, 0x53, 0x1a, 0xfd, 0xe5, 0x1a
-	.byte  0xf0, 0x7f, 0x3c, 0x02, 0x00, 0x06, 0x30, 0x09
-	.byte  0x0e, 0x12, 0x0e, 0xb0, 0x40, 0x09, 0xc2, 0x92
-	.byte  0xc2, 0x93, 0xc2, 0x09, 0x12, 0x0e, 0x7d, 0x22
-	.byte  0xa2, 0x1f, 0x92, 0x21, 0x85, 0x2f, 0x30, 0xa2
-	.byte  0x20, 0x92, 0x22, 0xc2, 0x23, 0xc2, 0x24, 0x02
-	.byte  0x06, 0xee, 0xef, 0xc4, 0x54, 0x0f, 0x90, 0x03
-	.byte  0x53, 0x93, 0xfe, 0xef, 0x54, 0x0f, 0x93, 0x2e
-	.byte  0xff, 0x22, 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02
-	.byte  0x54, 0xfe, 0xfe, 0xf0, 0x54, 0xfd, 0xf0, 0xee
-	.byte  0xf0, 0x22, 0x12, 0x0e, 0xa2, 0x12, 0x0c, 0xb3
-	.byte  0x92, 0x1b, 0x12, 0x0e, 0xa9, 0x20, 0x1b, 0xf2
-	.byte  0x22, 0x30, 0x05, 0x09, 0x20, 0x0e, 0x06, 0x20
-	.byte  0x02, 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x22, 0x30
-	.byte  0x03, 0x09, 0x20, 0x0a, 0x06, 0x20, 0x02, 0x03
-	.byte  0xd3, 0x80, 0x01, 0xc3, 0x22, 0xaa, 0x06, 0xea
-	.byte  0x24, 0xd0, 0xfd, 0xef, 0xfb, 0xaf, 0x34, 0x12
-	.byte  0x0b, 0xb4, 0x22, 0xef, 0x24, 0xfe, 0xfb, 0x7d
-	.byte  0xef, 0xaf, 0x34, 0x12, 0x0b, 0xb4, 0x22, 0xd2
-	.byte  0x02, 0xd2, 0x0d, 0xc2, 0x96, 0xd2, 0x10, 0xc2
-	.byte  0x94, 0x22, 0xef, 0x90, 0x02, 0xc9, 0x93, 0x6d
-	.byte  0x60, 0x02, 0x80, 0xfe, 0x22, 0x12, 0x0d, 0xf9
-	.byte  0x50, 0x04, 0xc2, 0x10, 0xd2, 0x94, 0x22, 0x12
-	.byte  0x0e, 0x07, 0x50, 0x04, 0xc2, 0x0d, 0xd2, 0x96
-	.byte  0x22, 0xe5, 0x89, 0x54, 0xf0, 0x44, 0x01, 0xf5
-	.byte  0x89, 0x22, 0x30, 0x8d, 0x04, 0xc2, 0x8c, 0xd3
-	.byte  0x22, 0xc3, 0x22, 0x30, 0xcf, 0x04, 0xc2, 0xca
-	.byte  0xd3, 0x22, 0xc3, 0x22, 0x12, 0x0e, 0xa2, 0x12
-	.byte  0x0e, 0xfa, 0x02, 0x0e, 0xa9, 0x12, 0x0e, 0xeb
-	.byte  0xc2, 0x0e, 0x02, 0x0e, 0x45, 0xc2, 0x02, 0x12
-	.byte  0x0e, 0x4f, 0x02, 0x0e, 0x45, 0xc2, 0x05, 0xd2
-	.byte  0x10, 0xc2, 0x94, 0x22, 0xc2, 0x03, 0xd2, 0x0d
-	.byte  0xc2, 0x96, 0x22, 0x90, 0xd0, 0x00, 0xe5, 0x1a
-	.byte  0xf0, 0x22, 0x30, 0x28, 0x03, 0x12, 0x0b, 0x90
-	.byte  0x22, 0x30, 0x28, 0x03, 0x12, 0x0d, 0x92, 0x22
-	.byte  0x90, 0xe0, 0x00, 0xe0, 0x13, 0x22, 0x53, 0x1a
-	.byte  0xfe, 0x02, 0x0e, 0x9b, 0x43, 0x1a, 0x01, 0x02
-	.byte  0x0e, 0x9b, 0x53, 0x1a, 0xfd, 0x02, 0x0e, 0x9b
-	.byte  0x43, 0x1a, 0x02, 0x02, 0x0e, 0x9b, 0x53, 0x1a
-	.byte  0xfb, 0x02, 0x0e, 0x9b, 0x43, 0x1a, 0x04, 0x02
-	.byte  0x0e, 0x9b, 0x53, 0x1a, 0x7f, 0x02, 0x0e, 0x9b
-	.byte  0x43, 0x1a, 0x80, 0x02, 0x0e, 0x9b, 0xd2, 0x05
-	.byte  0x02, 0x0e, 0x45, 0xc2, 0x0a, 0x02, 0x0e, 0x4f
-	.byte  0xd2, 0x03, 0x02, 0x0e, 0x4f, 0x8f, 0x1a, 0x02
-	.byte  0x0e, 0x9b, 0x7f, 0x06, 0x02, 0x0d, 0x67, 0x7f
-	.byte  0x04, 0x02, 0x0d, 0x67, 0xae, 0x36, 0xaf, 0x37
-	.byte  0x22, 0xe4, 0xf5, 0xc8, 0x22, 0x12, 0x0c, 0x1a
-	.byte  0x22, 0xc2, 0x0b, 0x22, 0xd2, 0x0b, 0x22, 0xc2
-	.byte  0x06, 0x22, 0xd2, 0x06, 0x22, 0xaf, 0x35, 0x22
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-	.byte  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
diff --git a/src/mainboard/dmp/Kconfig b/src/mainboard/dmp/Kconfig
deleted file mode 100644
index 055d88f533..0000000000
--- a/src/mainboard/dmp/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-if VENDOR_DMP
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/dmp/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/dmp/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	string
-	default "DMP"
-
-endif # VENDOR_DMP
diff --git a/src/mainboard/dmp/Kconfig.name b/src/mainboard/dmp/Kconfig.name
deleted file mode 100644
index ddce56a39f..0000000000
--- a/src/mainboard/dmp/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_DMP
-	bool "DMP"
diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig
deleted file mode 100644
index 9c4c178f69..0000000000
--- a/src/mainboard/dmp/vortex86ex/Kconfig
+++ /dev/null
@@ -1,1352 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-if BOARD_DMP_EX
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_DMP_VORTEX86EX
-	select SOC_DMP_VORTEX86EX
-	select HAVE_PIRQ_TABLE
-	select BOARD_ROMSIZE_KB_256
-	select ROMCC
-	select HAVE_DEBUG_RAM_SETUP
-
-config MAINBOARD_DIR
-	string
-	default dmp/vortex86ex
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Vortex86EX"
-
-config IRQ_SLOT_COUNT
-	int
-	default 12
-
-config ID_SECTION_OFFSET
-	# Vortex86 ROM fixed data areas used too big range, we need
-	# to move ID from default address to another place.
-	# 18K below top of ROM should be ok.
-	hex
-	default 0x4800
-
-# SPI I/O base address control.
-config I2C_BASE
-	hex
-	default 0xfb00
-
-menu "On-Chip Device Power Down Control"
-
-	config TEMP_POWERDOWN
-	bool "Temperature sensor power-down"
-
-	config SATA_POWERDOWN
-	bool "SATA power-down"
-
-	config ADC_POWERDOWN
-	bool "ADC power-down"
-
-	config PCIE0_POWERDOWN
-	bool "PCIE0 power-down"
-
-	config MAC_POWERDOWN
-	bool "MAC power-down"
-
-	config USB1_POWERDOWN
-	bool "USB2.0 Host Controller 1 power-down"
-
-	config IDE_POWERDOWN
-	bool "IDE power-down"
-
-endmenu
-
-menu "Watchdog Timer setting"
-
-config WDT1_INITIALIZE
-	bool "Initialize WDT1"
-	default n
-
-config WDT1_ENABLE
-	depends on WDT1_INITIALIZE
-	bool "Enable WDT1"
-	default n
-
-choice
-	depends on WDT1_INITIALIZE
-	prompt "WDT1 Signal Select"
-	default WDT1_SIGNAL_RESET
-
-config WDT1_SINGAL_NMI
-	bool "NMI"
-config WDT1_SIGNAL_RESET
-	bool "Reset"
-config WDT1_SIGNAL_SMI
-	bool "SMI"
-
-endchoice
-
-endmenu
-
-menu "IDE controller setting"
-
-choice
-	prompt "Operation Mode"
-	default IDE_NATIVE_MODE
-
-config IDE_NATIVE_MODE
-	bool "Native Mode"
-config IDE_LEGACY_MODE
-	bool "Legacy Mode"
-
-endchoice
-
-config IDE1_ENABLE
-	bool "IDE Primary channel Enable"
-	default y
-
-config IDE2_ENABLE
-	bool "IDE Secondary channel Enable"
-	default y
-
-config IDE_STANDARD_COMPATIBLE
-	bool "Standard IDE Compatible"
-	default n
-	help
-	  Built-in IDE controller PCI vendor/device ID is 17F3:1012, which
-	  is not recognized by some OSes.
-
-	  This option can change IDE controller PCI vendor/device ID to
-	  other value for software compatibility.
-
-config IDE_COMPATIBLE_SELECTION
-	depends on IDE_STANDARD_COMPATIBLE
-	hex "IDE Compatible Selection"
-	default 0x808624db
-	help
-	  IDE controller PCI vendor/device ID value setting.
-
-	  Higher 16-bit is vendor ID, lower 16-bit is device ID.
-
-endmenu
-
-# GPIO setting :
-menu "GPIO setting"
-
-# Begin of GPIO0
-config GPIO_P0_ENABLE
-	bool "GPIO port 0 Enable"
-	default n
-
-config GPIO_P0_DATA_ADDR
-	hex "GPIO port 0 data address"
-	depends on GPIO_P0_ENABLE
-
-config GPIO_P0_DIR_ADDR
-	hex "GPIO port 0 direction address"
-	depends on GPIO_P0_ENABLE
-
-config GPIO_P0_INIT_DIR
-	hex "GPIO port 0 initial direction"
-	default 0x00
-	depends on GPIO_P0_ENABLE
-
-config GPIO_P0_INIT_DATA
-	hex "GPIO port 0 initial data"
-	depends on GPIO_P0_ENABLE
-# end of GPIO0
-
-# Begin of GPIO1
-config GPIO_P1_ENABLE
-	bool "GPIO port 1 Enable"
-	default n
-
-config GPIO_P1_DATA_ADDR
-	hex "GPIO port 1 data address"
-	depends on GPIO_P1_ENABLE
-
-config GPIO_P1_DIR_ADDR
-	hex "GPIO port 1 direction address"
-	depends on GPIO_P1_ENABLE
-
-config GPIO_P1_INIT_DIR
-	hex "GPIO port 1 initial direction"
-	default 0x00
-	depends on GPIO_P1_ENABLE
-
-config GPIO_P1_INIT_DATA
-	hex "GPIO port 1 initial data"
-	depends on GPIO_P1_ENABLE
-# end of GPIO1
-
-# Begin of GPIO2
-config GPIO_P2_ENABLE
-	bool "GPIO port 2 Enable"
-	default n
-
-config GPIO_P2_DATA_ADDR
-	hex "GPIO port 2 data address"
-	depends on GPIO_P2_ENABLE
-
-config GPIO_P2_DIR_ADDR
-	hex "GPIO port 2 direction address"
-	depends on GPIO_P2_ENABLE
-
-config GPIO_P2_INIT_DIR
-	hex "GPIO port 2 initial direction"
-	default 0x00
-	depends on GPIO_P2_ENABLE
-
-config GPIO_P2_INIT_DATA
-	hex "GPIO port 2 initial data"
-	depends on GPIO_P2_ENABLE
-# end of GPIO2
-
-# Begin of GPIO3
-config GPIO_P3_ENABLE
-	bool "GPIO port 3 Enable"
-	default n
-
-config GPIO_P3_DATA_ADDR
-	hex "GPIO port 3 data address"
-	depends on GPIO_P3_ENABLE
-
-config GPIO_P3_DIR_ADDR
-	hex "GPIO port 3 direction address"
-	depends on GPIO_P3_ENABLE
-
-config GPIO_P3_INIT_DIR
-	hex "GPIO port 3 initial direction"
-	default 0x00
-	depends on GPIO_P3_ENABLE
-
-config GPIO_P3_INIT_DATA
-	hex "GPIO port 3 initial data"
-	depends on GPIO_P3_ENABLE
-# end of GPIO3
-
-# Begin of GPIO4
-config GPIO_P4_ENABLE
-	bool "GPIO port 4 Enable"
-	default n
-
-config GPIO_P4_DATA_ADDR
-	hex "GPIO port 4 data address"
-	depends on GPIO_P4_ENABLE
-
-config GPIO_P4_DIR_ADDR
-	hex "GPIO port 4 direction address"
-	depends on GPIO_P4_ENABLE
-
-config GPIO_P4_INIT_DIR
-	hex "GPIO port 4 initial direction"
-	default 0x00
-	depends on GPIO_P4_ENABLE
-
-config GPIO_P4_INIT_DATA
-	hex "GPIO port 4 initial data"
-	depends on GPIO_P4_ENABLE
-# end of GPIO4
-
-# Begin of GPIO5
-config GPIO_P5_ENABLE
-	bool "GPIO port 5 Enable"
-	default n
-
-config GPIO_P5_DATA_ADDR
-	hex "GPIO port 5 data address"
-	depends on GPIO_P5_ENABLE
-
-config GPIO_P5_DIR_ADDR
-	hex "GPIO port 5 direction address"
-	depends on GPIO_P5_ENABLE
-
-config GPIO_P5_INIT_DIR
-	hex "GPIO port 5 initial direction"
-	default 0x00
-	depends on GPIO_P5_ENABLE
-
-config GPIO_P5_INIT_DATA
-	hex "GPIO port 5 initial data"
-	depends on GPIO_P5_ENABLE
-# end of GPIO5
-
-# Begin of GPIO6
-config GPIO_P6_ENABLE
-	bool "GPIO port 6 Enable"
-	default n
-
-config GPIO_P6_DATA_ADDR
-	hex "GPIO port 6 data address"
-	depends on GPIO_P6_ENABLE
-
-config GPIO_P6_DIR_ADDR
-	hex "GPIO port 6 direction address"
-	depends on GPIO_P6_ENABLE
-
-config GPIO_P6_INIT_DIR
-	hex "GPIO port 6 initial direction"
-	default 0x00
-	depends on GPIO_P6_ENABLE
-
-config GPIO_P6_INIT_DATA
-	hex "GPIO port 6 initial data"
-	depends on GPIO_P6_ENABLE
-# end of GPIO6
-
-# Begin of GPIO7
-config GPIO_P7_ENABLE
-	bool "GPIO port 7 Enable"
-	default n
-
-config GPIO_P7_DATA_ADDR
-	hex "GPIO port 7 data address"
-	depends on GPIO_P7_ENABLE
-
-config GPIO_P7_DIR_ADDR
-	hex "GPIO port 7 direction address"
-	depends on GPIO_P7_ENABLE
-
-config GPIO_P7_INIT_DIR
-	hex "GPIO port 7 initial direction"
-	default 0x00
-	depends on GPIO_P7_ENABLE
-
-config GPIO_P7_INIT_DATA
-	hex "GPIO port 7 initial data"
-	depends on GPIO_P7_ENABLE
-# end of GPIO7
-
-# Begin of GPIO8
-config GPIO_P8_ENABLE
-	bool "GPIO port 8 Enable"
-	default n
-
-config GPIO_P8_DATA_ADDR
-	hex "GPIO port 8 data address"
-	depends on GPIO_P8_ENABLE
-
-config GPIO_P8_DIR_ADDR
-	hex "GPIO port 8 direction address"
-	depends on GPIO_P8_ENABLE
-
-config GPIO_P8_INIT_DIR
-	hex "GPIO port 8 initial direction"
-	default 0x00
-	depends on GPIO_P8_ENABLE
-
-config GPIO_P8_INIT_DATA
-	hex "GPIO port 8 initial data"
-	depends on GPIO_P8_ENABLE
-# end of GPIO8
-
-# Begin of GPIO9
-config GPIO_P9_ENABLE
-	bool "GPIO port 9 Enable"
-	default n
-
-config GPIO_P9_DATA_ADDR
-	hex "GPIO port 9 data address"
-	depends on GPIO_P9_ENABLE
-
-config GPIO_P9_DIR_ADDR
-	hex "GPIO port 9 direction address"
-	depends on GPIO_P9_ENABLE
-
-config GPIO_P9_INIT_DIR
-	hex "GPIO port 9 initial direction"
-	default 0x00
-	depends on GPIO_P9_ENABLE
-
-config GPIO_P9_INIT_DATA
-	hex "GPIO port 9 initial data"
-	depends on GPIO_P9_ENABLE
-# end of GPIO9
-
-endmenu
-
-# UART setting :
-menu "UART setting"
-
-# Begin of UART1
-config UART1_ENABLE
-	bool "UART1 Enable"
-	default y
-
-choice
-	prompt "UART1 I/O port"
-	default UART1_IO_PORT_3F8
-	depends on UART1_ENABLE
-
-config UART1_IO_PORT_3F8
-	bool "0x3f8, COM1"
-config UART1_IO_PORT_2F8
-	bool "0x2f8, COM2"
-config UART1_IO_PORT_3E8
-	bool "0x3e8, COM3"
-config UART1_IO_PORT_2E8
-	bool "0x2e8, COM4"
-config UART1_IO_PORT_OTHER
-	bool "Other"
-
-endchoice
-
-config UART1_IO_PORT_OTHER_INPUT
-	hex "UART1 I/O port"
-	depends on UART1_ENABLE && UART1_IO_PORT_OTHER
-
-config UART1_IO
-	hex
-	depends on UART1_ENABLE
-	default 0x3f8 if UART1_IO_PORT_3F8
-	default 0x2f8 if UART1_IO_PORT_2F8
-	default 0x3e8 if UART1_IO_PORT_3E8
-	default 0x2e8 if UART1_IO_PORT_2E8
-	default UART1_IO_PORT_OTHER_INPUT if UART1_IO_PORT_OTHER
-
-choice
-	prompt "UART1 IRQ"
-	default UART1_IRQ4
-	depends on UART1_ENABLE
-
-config UART1_IRQ_DISABLE
-	bool "Disable"
-config UART1_IRQ3
-	bool "IRQ3, COM2"
-config UART1_IRQ4
-	bool "IRQ4, COM1"
-config UART1_IRQ5
-	bool "IRQ5"
-config UART1_IRQ6
-	bool "IRQ6"
-config UART1_IRQ7
-	bool "IRQ7"
-config UART1_IRQ9
-	bool "IRQ9"
-config UART1_IRQ10
-	bool "IRQ10, COM3"
-config UART1_IRQ11
-	bool "IRQ11, COM4"
-config UART1_IRQ12
-	bool "IRQ12"
-config UART1_IRQ14
-	bool "IRQ14"
-config UART1_IRQ15
-	bool "IRQ15"
-
-endchoice
-
-config UART1_IRQ
-	int
-	depends on UART1_ENABLE
-	default 0 if UART1_IRQ_DISABLE
-	default 3 if UART1_IRQ3
-	default 4 if UART1_IRQ4
-	default 5 if UART1_IRQ5
-	default 6 if UART1_IRQ6
-	default 7 if UART1_IRQ7
-	default 9 if UART1_IRQ9
-	default 10 if UART1_IRQ10
-	default 11 if UART1_IRQ11
-	default 12 if UART1_IRQ12
-	default 14 if UART1_IRQ14
-	default 15 if UART1_IRQ15
-
-# end of UART1
-
-# Begin of UART2
-config UART2_ENABLE
-	bool "UART2 Enable"
-	default y
-
-choice
-	prompt "UART2 I/O port"
-	default UART2_IO_PORT_2F8
-	depends on UART2_ENABLE
-
-config UART2_IO_PORT_3F8
-	bool "0x3f8, COM1"
-config UART2_IO_PORT_2F8
-	bool "0x2f8, COM2"
-config UART2_IO_PORT_3E8
-	bool "0x3e8, COM3"
-config UART2_IO_PORT_2E8
-	bool "0x2e8, COM4"
-config UART2_IO_PORT_OTHER
-	bool "Other"
-
-endchoice
-
-config UART2_IO_PORT_OTHER_INPUT
-	hex "UART2 I/O port"
-	depends on UART2_ENABLE && UART2_IO_PORT_OTHER
-
-config UART2_IO
-	hex
-	depends on UART2_ENABLE
-	default 0x3f8 if UART2_IO_PORT_3F8
-	default 0x2f8 if UART2_IO_PORT_2F8
-	default 0x3e8 if UART2_IO_PORT_3E8
-	default 0x2e8 if UART2_IO_PORT_2E8
-	default UART2_IO_PORT_OTHER_INPUT if UART2_IO_PORT_OTHER
-
-choice
-	prompt "UART2 IRQ"
-	default UART2_IRQ3
-	depends on UART2_ENABLE
-
-config UART2_IRQ_DISABLE
-	bool "Disable"
-config UART2_IRQ3
-	bool "IRQ3, COM2"
-config UART2_IRQ4
-	bool "IRQ4, COM1"
-config UART2_IRQ5
-	bool "IRQ5"
-config UART2_IRQ6
-	bool "IRQ6"
-config UART2_IRQ7
-	bool "IRQ7"
-config UART2_IRQ9
-	bool "IRQ9"
-config UART2_IRQ10
-	bool "IRQ10, COM3"
-config UART2_IRQ11
-	bool "IRQ11, COM4"
-config UART2_IRQ12
-	bool "IRQ12"
-config UART2_IRQ14
-	bool "IRQ14"
-config UART2_IRQ15
-	bool "IRQ15"
-
-endchoice
-
-config UART2_IRQ
-	int
-	depends on UART2_ENABLE
-	default 0 if UART2_IRQ_DISABLE
-	default 3 if UART2_IRQ3
-	default 4 if UART2_IRQ4
-	default 5 if UART2_IRQ5
-	default 6 if UART2_IRQ6
-	default 7 if UART2_IRQ7
-	default 9 if UART2_IRQ9
-	default 10 if UART2_IRQ10
-	default 11 if UART2_IRQ11
-	default 12 if UART2_IRQ12
-	default 14 if UART2_IRQ14
-	default 15 if UART2_IRQ15
-
-# end of UART2
-
-# Begin of UART3
-config UART3_ENABLE
-	bool "UART3 Enable"
-	default y
-
-choice
-	prompt "UART3 I/O port"
-	default UART3_IO_PORT_3E8
-	depends on UART3_ENABLE
-
-config UART3_IO_PORT_3F8
-	bool "0x3f8, COM1"
-config UART3_IO_PORT_2F8
-	bool "0x2f8, COM2"
-config UART3_IO_PORT_3E8
-	bool "0x3e8, COM3"
-config UART3_IO_PORT_2E8
-	bool "0x2e8, COM4"
-config UART3_IO_PORT_OTHER
-	bool "Other"
-
-endchoice
-
-config UART3_IO_PORT_OTHER_INPUT
-	hex "UART3 I/O port"
-	depends on UART3_ENABLE && UART3_IO_PORT_OTHER
-
-config UART3_IO
-	hex
-	depends on UART3_ENABLE
-	default 0x3f8 if UART3_IO_PORT_3F8
-	default 0x2f8 if UART3_IO_PORT_2F8
-	default 0x3e8 if UART3_IO_PORT_3E8
-	default 0x2e8 if UART3_IO_PORT_2E8
-	default UART3_IO_PORT_OTHER_INPUT if UART3_IO_PORT_OTHER
-
-choice
-	prompt "UART3 IRQ"
-	default UART3_IRQ10
-	depends on UART3_ENABLE
-
-config UART3_IRQ_DISABLE
-	bool "Disable"
-config UART3_IRQ3
-	bool "IRQ3, COM2"
-config UART3_IRQ4
-	bool "IRQ4, COM1"
-config UART3_IRQ5
-	bool "IRQ5"
-config UART3_IRQ6
-	bool "IRQ6"
-config UART3_IRQ7
-	bool "IRQ7"
-config UART3_IRQ9
-	bool "IRQ9"
-config UART3_IRQ10
-	bool "IRQ10, COM3"
-config UART3_IRQ11
-	bool "IRQ11, COM4"
-config UART3_IRQ12
-	bool "IRQ12"
-config UART3_IRQ14
-	bool "IRQ14"
-config UART3_IRQ15
-	bool "IRQ15"
-
-endchoice
-
-config UART3_IRQ
-	int
-	depends on UART3_ENABLE
-	default 0 if UART3_IRQ_DISABLE
-	default 3 if UART3_IRQ3
-	default 4 if UART3_IRQ4
-	default 5 if UART3_IRQ5
-	default 6 if UART3_IRQ6
-	default 7 if UART3_IRQ7
-	default 9 if UART3_IRQ9
-	default 10 if UART3_IRQ10
-	default 11 if UART3_IRQ11
-	default 12 if UART3_IRQ12
-	default 14 if UART3_IRQ14
-	default 15 if UART3_IRQ15
-
-# end of UART3
-
-# Begin of UART4
-config UART4_ENABLE
-	bool "UART4 Enable"
-	default y
-
-choice
-	prompt "UART4 I/O port"
-	default UART4_IO_PORT_2E8
-	depends on UART4_ENABLE
-
-config UART4_IO_PORT_3F8
-	bool "0x3f8, COM1"
-config UART4_IO_PORT_2F8
-	bool "0x2f8, COM2"
-config UART4_IO_PORT_3E8
-	bool "0x3e8, COM3"
-config UART4_IO_PORT_2E8
-	bool "0x2e8, COM4"
-config UART4_IO_PORT_OTHER
-	bool "Other"
-
-endchoice
-
-config UART4_IO_PORT_OTHER_INPUT
-	hex "UART4 I/O port"
-	depends on UART4_ENABLE && UART4_IO_PORT_OTHER
-
-config UART4_IO
-	hex
-	depends on UART4_ENABLE
-	default 0x3f8 if UART4_IO_PORT_3F8
-	default 0x2f8 if UART4_IO_PORT_2F8
-	default 0x3e8 if UART4_IO_PORT_3E8
-	default 0x2e8 if UART4_IO_PORT_2E8
-	default UART4_IO_PORT_OTHER_INPUT if UART4_IO_PORT_OTHER
-
-choice
-	prompt "UART4 IRQ"
-	default UART4_IRQ11
-	depends on UART4_ENABLE
-
-config UART4_IRQ_DISABLE
-	bool "Disable"
-config UART4_IRQ3
-	bool "IRQ3, COM2"
-config UART4_IRQ4
-	bool "IRQ4, COM1"
-config UART4_IRQ5
-	bool "IRQ5"
-config UART4_IRQ6
-	bool "IRQ6"
-config UART4_IRQ7
-	bool "IRQ7"
-config UART4_IRQ9
-	bool "IRQ9"
-config UART4_IRQ10
-	bool "IRQ10, COM3"
-config UART4_IRQ11
-	bool "IRQ11, COM4"
-config UART4_IRQ12
-	bool "IRQ12"
-config UART4_IRQ14
-	bool "IRQ14"
-config UART4_IRQ15
-	bool "IRQ15"
-
-endchoice
-
-config UART4_IRQ
-	int
-	depends on UART4_ENABLE
-	default 0 if UART4_IRQ_DISABLE
-	default 3 if UART4_IRQ3
-	default 4 if UART4_IRQ4
-	default 5 if UART4_IRQ5
-	default 6 if UART4_IRQ6
-	default 7 if UART4_IRQ7
-	default 9 if UART4_IRQ9
-	default 10 if UART4_IRQ10
-	default 11 if UART4_IRQ11
-	default 12 if UART4_IRQ12
-	default 14 if UART4_IRQ14
-	default 15 if UART4_IRQ15
-
-# end of UART4
-
-# Begin of UART5
-config UART5_ENABLE
-	bool "UART5 Enable"
-	default n
-
-choice
-	prompt "UART5 I/O port"
-	default UART5_IO_PORT_OTHER
-	depends on UART5_ENABLE
-
-config UART5_IO_PORT_3F8
-	bool "0x3f8, COM1"
-config UART5_IO_PORT_2F8
-	bool "0x2f8, COM2"
-config UART5_IO_PORT_3E8
-	bool "0x3e8, COM3"
-config UART5_IO_PORT_2E8
-	bool "0x2e8, COM4"
-config UART5_IO_PORT_OTHER
-	bool "Other"
-
-endchoice
-
-config UART5_IO_PORT_OTHER_INPUT
-	hex "UART5 I/O port"
-	depends on UART5_ENABLE && UART5_IO_PORT_OTHER
-
-config UART5_IO
-	hex
-	depends on UART5_ENABLE
-	default 0x3f8 if UART5_IO_PORT_3F8
-	default 0x2f8 if UART5_IO_PORT_2F8
-	default 0x3e8 if UART5_IO_PORT_3E8
-	default 0x2e8 if UART5_IO_PORT_2E8
-	default UART5_IO_PORT_OTHER_INPUT if UART5_IO_PORT_OTHER
-
-choice
-	prompt "UART5 IRQ"
-	default UART5_IRQ_DISABLE
-	depends on UART5_ENABLE
-
-config UART5_IRQ_DISABLE
-	bool "Disable"
-config UART5_IRQ3
-	bool "IRQ3, COM2"
-config UART5_IRQ4
-	bool "IRQ4, COM1"
-config UART5_IRQ5
-	bool "IRQ5"
-config UART5_IRQ6
-	bool "IRQ6"
-config UART5_IRQ7
-	bool "IRQ7"
-config UART5_IRQ9
-	bool "IRQ9"
-config UART5_IRQ10
-	bool "IRQ10, COM3"
-config UART5_IRQ11
-	bool "IRQ11, COM4"
-config UART5_IRQ12
-	bool "IRQ12"
-config UART5_IRQ14
-	bool "IRQ14"
-config UART5_IRQ15
-	bool "IRQ15"
-
-endchoice
-
-config UART5_IRQ
-	int
-	depends on UART5_ENABLE
-	default 0 if UART5_IRQ_DISABLE
-	default 3 if UART5_IRQ3
-	default 4 if UART5_IRQ4
-	default 5 if UART5_IRQ5
-	default 6 if UART5_IRQ6
-	default 7 if UART5_IRQ7
-	default 9 if UART5_IRQ9
-	default 10 if UART5_IRQ10
-	default 11 if UART5_IRQ11
-	default 12 if UART5_IRQ12
-	default 14 if UART5_IRQ14
-	default 15 if UART5_IRQ15
-
-# end of UART5
-
-# Begin of UART6
-config UART6_ENABLE
-	bool "UART6 Enable"
-	default n
-
-choice
-	prompt "UART6 I/O port"
-	default UART6_IO_PORT_OTHER
-	depends on UART6_ENABLE
-
-config UART6_IO_PORT_3F8
-	bool "0x3f8, COM1"
-config UART6_IO_PORT_2F8
-	bool "0x2f8, COM2"
-config UART6_IO_PORT_3E8
-	bool "0x3e8, COM3"
-config UART6_IO_PORT_2E8
-	bool "0x2e8, COM4"
-config UART6_IO_PORT_OTHER
-	bool "Other"
-
-endchoice
-
-config UART6_IO_PORT_OTHER_INPUT
-	hex "UART6 I/O port"
-	depends on UART6_ENABLE && UART6_IO_PORT_OTHER
-
-config UART6_IO
-	hex
-	depends on UART6_ENABLE
-	default 0x3f8 if UART6_IO_PORT_3F8
-	default 0x2f8 if UART6_IO_PORT_2F8
-	default 0x3e8 if UART6_IO_PORT_3E8
-	default 0x2e8 if UART6_IO_PORT_2E8
-	default UART6_IO_PORT_OTHER_INPUT if UART6_IO_PORT_OTHER
-
-choice
-	prompt "UART6 IRQ"
-	default UART6_IRQ_DISABLE
-	depends on UART6_ENABLE
-
-config UART6_IRQ_DISABLE
-	bool "Disable"
-config UART6_IRQ3
-	bool "IRQ3, COM2"
-config UART6_IRQ4
-	bool "IRQ4, COM1"
-config UART6_IRQ5
-	bool "IRQ5"
-config UART6_IRQ6
-	bool "IRQ6"
-config UART6_IRQ7
-	bool "IRQ7"
-config UART6_IRQ9
-	bool "IRQ9"
-config UART6_IRQ10
-	bool "IRQ10, COM3"
-config UART6_IRQ11
-	bool "IRQ11, COM4"
-config UART6_IRQ12
-	bool "IRQ12"
-config UART6_IRQ14
-	bool "IRQ14"
-config UART6_IRQ15
-	bool "IRQ15"
-
-endchoice
-
-config UART6_IRQ
-	int
-	depends on UART6_ENABLE
-	default 0 if UART6_IRQ_DISABLE
-	default 3 if UART6_IRQ3
-	default 4 if UART6_IRQ4
-	default 5 if UART6_IRQ5
-	default 6 if UART6_IRQ6
-	default 7 if UART6_IRQ7
-	default 9 if UART6_IRQ9
-	default 10 if UART6_IRQ10
-	default 11 if UART6_IRQ11
-	default 12 if UART6_IRQ12
-	default 14 if UART6_IRQ14
-	default 15 if UART6_IRQ15
-
-# end of UART6
-
-# Begin of UART7
-config UART7_ENABLE
-	bool "UART7 Enable"
-	default n
-
-choice
-	prompt "UART7 I/O port"
-	default UART7_IO_PORT_OTHER
-	depends on UART7_ENABLE
-
-config UART7_IO_PORT_3F8
-	bool "0x3f8, COM1"
-config UART7_IO_PORT_2F8
-	bool "0x2f8, COM2"
-config UART7_IO_PORT_3E8
-	bool "0x3e8, COM3"
-config UART7_IO_PORT_2E8
-	bool "0x2e8, COM4"
-config UART7_IO_PORT_OTHER
-	bool "Other"
-
-endchoice
-
-config UART7_IO_PORT_OTHER_INPUT
-	hex "UART7 I/O port"
-	depends on UART7_ENABLE && UART7_IO_PORT_OTHER
-
-config UART7_IO
-	hex
-	depends on UART7_ENABLE
-	default 0x3f8 if UART7_IO_PORT_3F8
-	default 0x2f8 if UART7_IO_PORT_2F8
-	default 0x3e8 if UART7_IO_PORT_3E8
-	default 0x2e8 if UART7_IO_PORT_2E8
-	default UART7_IO_PORT_OTHER_INPUT if UART7_IO_PORT_OTHER
-
-choice
-	prompt "UART7 IRQ"
-	default UART7_IRQ_DISABLE
-	depends on UART7_ENABLE
-
-config UART7_IRQ_DISABLE
-	bool "Disable"
-config UART7_IRQ3
-	bool "IRQ3, COM2"
-config UART7_IRQ4
-	bool "IRQ4, COM1"
-config UART7_IRQ5
-	bool "IRQ5"
-config UART7_IRQ6
-	bool "IRQ6"
-config UART7_IRQ7
-	bool "IRQ7"
-config UART7_IRQ9
-	bool "IRQ9"
-config UART7_IRQ10
-	bool "IRQ10, COM3"
-config UART7_IRQ11
-	bool "IRQ11, COM4"
-config UART7_IRQ12
-	bool "IRQ12"
-config UART7_IRQ14
-	bool "IRQ14"
-config UART7_IRQ15
-	bool "IRQ15"
-
-endchoice
-
-config UART7_IRQ
-	int
-	depends on UART7_ENABLE
-	default 0 if UART7_IRQ_DISABLE
-	default 3 if UART7_IRQ3
-	default 4 if UART7_IRQ4
-	default 5 if UART7_IRQ5
-	default 6 if UART7_IRQ6
-	default 7 if UART7_IRQ7
-	default 9 if UART7_IRQ9
-	default 10 if UART7_IRQ10
-	default 11 if UART7_IRQ11
-	default 12 if UART7_IRQ12
-	default 14 if UART7_IRQ14
-	default 15 if UART7_IRQ15
-
-# end of UART7
-
-# Begin of UART8
-config UART8_ENABLE
-	bool "UART8 Enable"
-	default n
-
-choice
-	prompt "UART8 I/O port"
-	default UART8_IO_PORT_OTHER
-	depends on UART8_ENABLE
-
-config UART8_IO_PORT_3F8
-	bool "0x3f8, COM1"
-config UART8_IO_PORT_2F8
-	bool "0x2f8, COM2"
-config UART8_IO_PORT_3E8
-	bool "0x3e8, COM3"
-config UART8_IO_PORT_2E8
-	bool "0x2e8, COM4"
-config UART8_IO_PORT_OTHER
-	bool "Other"
-
-endchoice
-
-config UART8_IO_PORT_OTHER_INPUT
-	hex "UART8 I/O port"
-	depends on UART8_ENABLE && UART8_IO_PORT_OTHER
-
-config UART8_IO
-	hex
-	depends on UART8_ENABLE
-	default 0x3f8 if UART8_IO_PORT_3F8
-	default 0x2f8 if UART8_IO_PORT_2F8
-	default 0x3e8 if UART8_IO_PORT_3E8
-	default 0x2e8 if UART8_IO_PORT_2E8
-	default UART8_IO_PORT_OTHER_INPUT if UART8_IO_PORT_OTHER
-
-choice
-	prompt "UART8 IRQ"
-	default UART8_IRQ_DISABLE
-	depends on UART8_ENABLE
-
-config UART8_IRQ_DISABLE
-	bool "Disable"
-config UART8_IRQ3
-	bool "IRQ3, COM2"
-config UART8_IRQ4
-	bool "IRQ4, COM1"
-config UART8_IRQ5
-	bool "IRQ5"
-config UART8_IRQ6
-	bool "IRQ6"
-config UART8_IRQ7
-	bool "IRQ7"
-config UART8_IRQ9
-	bool "IRQ9"
-config UART8_IRQ10
-	bool "IRQ10, COM3"
-config UART8_IRQ11
-	bool "IRQ11, COM4"
-config UART8_IRQ12
-	bool "IRQ12"
-config UART8_IRQ14
-	bool "IRQ14"
-config UART8_IRQ15
-	bool "IRQ15"
-
-endchoice
-
-config UART8_IRQ
-	int
-	depends on UART8_ENABLE
-	default 0 if UART8_IRQ_DISABLE
-	default 3 if UART8_IRQ3
-	default 4 if UART8_IRQ4
-	default 5 if UART8_IRQ5
-	default 6 if UART8_IRQ6
-	default 7 if UART8_IRQ7
-	default 9 if UART8_IRQ9
-	default 10 if UART8_IRQ10
-	default 11 if UART8_IRQ11
-	default 12 if UART8_IRQ12
-	default 14 if UART8_IRQ14
-	default 15 if UART8_IRQ15
-
-# end of UART8
-
-# Begin of UART9
-config UART9_ENABLE
-	bool "UART9 Enable"
-	default n
-
-choice
-	prompt "UART9 I/O port"
-	default UART9_IO_PORT_OTHER
-	depends on UART9_ENABLE
-
-config UART9_IO_PORT_3F8
-	bool "0x3f8, COM1"
-config UART9_IO_PORT_2F8
-	bool "0x2f8, COM2"
-config UART9_IO_PORT_3E8
-	bool "0x3e8, COM3"
-config UART9_IO_PORT_2E8
-	bool "0x2e8, COM4"
-config UART9_IO_PORT_OTHER
-	bool "Other"
-
-endchoice
-
-config UART9_IO_PORT_OTHER_INPUT
-	hex "UART9 I/O port"
-	depends on UART9_ENABLE && UART9_IO_PORT_OTHER
-
-config UART9_IO
-	hex
-	depends on UART9_ENABLE
-	default 0x3f8 if UART9_IO_PORT_3F8
-	default 0x2f8 if UART9_IO_PORT_2F8
-	default 0x3e8 if UART9_IO_PORT_3E8
-	default 0x2e8 if UART9_IO_PORT_2E8
-	default UART9_IO_PORT_OTHER_INPUT if UART9_IO_PORT_OTHER
-
-choice
-	prompt "UART9 IRQ"
-	default UART9_IRQ_DISABLE
-	depends on UART9_ENABLE
-
-config UART9_IRQ_DISABLE
-	bool "Disable"
-config UART9_IRQ3
-	bool "IRQ3, COM2"
-config UART9_IRQ4
-	bool "IRQ4, COM1"
-config UART9_IRQ5
-	bool "IRQ5"
-config UART9_IRQ6
-	bool "IRQ6"
-config UART9_IRQ7
-	bool "IRQ7"
-config UART9_IRQ9
-	bool "IRQ9"
-config UART9_IRQ10
-	bool "IRQ10, COM3"
-config UART9_IRQ11
-	bool "IRQ11, COM4"
-config UART9_IRQ12
-	bool "IRQ12"
-config UART9_IRQ14
-	bool "IRQ14"
-config UART9_IRQ15
-	bool "IRQ15"
-
-endchoice
-
-config UART9_IRQ
-	int
-	depends on UART9_ENABLE
-	default 0 if UART9_IRQ_DISABLE
-	default 3 if UART9_IRQ3
-	default 4 if UART9_IRQ4
-	default 5 if UART9_IRQ5
-	default 6 if UART9_IRQ6
-	default 7 if UART9_IRQ7
-	default 9 if UART9_IRQ9
-	default 10 if UART9_IRQ10
-	default 11 if UART9_IRQ11
-	default 12 if UART9_IRQ12
-	default 14 if UART9_IRQ14
-	default 15 if UART9_IRQ15
-
-# end of UART9
-
-# Begin of UART10
-config UART10_ENABLE
-	bool "UART10 Enable"
-	default n
-
-choice
-	prompt "UART10 I/O port"
-	default UART10_IO_PORT_OTHER
-	depends on UART10_ENABLE
-
-config UART10_IO_PORT_3F8
-	bool "0x3f8, COM1"
-config UART10_IO_PORT_2F8
-	bool "0x2f8, COM2"
-config UART10_IO_PORT_3E8
-	bool "0x3e8, COM3"
-config UART10_IO_PORT_2E8
-	bool "0x2e8, COM4"
-config UART10_IO_PORT_OTHER
-	bool "Other"
-
-endchoice
-
-config UART10_IO_PORT_OTHER_INPUT
-	hex "UART10 I/O port"
-	depends on UART10_ENABLE && UART10_IO_PORT_OTHER
-
-config UART10_IO
-	hex
-	depends on UART10_ENABLE
-	default 0x3f8 if UART10_IO_PORT_3F8
-	default 0x2f8 if UART10_IO_PORT_2F8
-	default 0x3e8 if UART10_IO_PORT_3E8
-	default 0x2e8 if UART10_IO_PORT_2E8
-	default UART10_IO_PORT_OTHER_INPUT if UART10_IO_PORT_OTHER
-
-choice
-	prompt "UART10 IRQ"
-	default UART10_IRQ_DISABLE
-	depends on UART10_ENABLE
-
-config UART10_IRQ_DISABLE
-	bool "Disable"
-config UART10_IRQ3
-	bool "IRQ3, COM2"
-config UART10_IRQ4
-	bool "IRQ4, COM1"
-config UART10_IRQ5
-	bool "IRQ5"
-config UART10_IRQ6
-	bool "IRQ6"
-config UART10_IRQ7
-	bool "IRQ7"
-config UART10_IRQ9
-	bool "IRQ9"
-config UART10_IRQ10
-	bool "IRQ10, COM3"
-config UART10_IRQ11
-	bool "IRQ11, COM4"
-config UART10_IRQ12
-	bool "IRQ12"
-config UART10_IRQ14
-	bool "IRQ14"
-config UART10_IRQ15
-	bool "IRQ15"
-
-endchoice
-
-config UART10_IRQ
-	int
-	depends on UART10_ENABLE
-	default 0 if UART10_IRQ_DISABLE
-	default 3 if UART10_IRQ3
-	default 4 if UART10_IRQ4
-	default 5 if UART10_IRQ5
-	default 6 if UART10_IRQ6
-	default 7 if UART10_IRQ7
-	default 9 if UART10_IRQ9
-	default 10 if UART10_IRQ10
-	default 11 if UART10_IRQ11
-	default 12 if UART10_IRQ12
-	default 14 if UART10_IRQ14
-	default 15 if UART10_IRQ15
-
-# end of UART10
-
-endmenu
-
-# LPT setting :
-menu "LPT setting"
-
-# Begin of LPT
-config LPT_ENABLE
-	bool "LPT Enable"
-	default n
-
-choice
-	prompt "LPT I/O port"
-	default LPT_IO_PORT_278
-	depends on LPT_ENABLE
-
-config LPT_IO_PORT_378
-	bool "0x378, LPT1"
-config LPT_IO_PORT_278
-	bool "0x278, LPT2"
-config LPT_IO_PORT_OTHER
-	bool "Other"
-
-endchoice
-
-config LPT_IO_PORT_OTHER_INPUT
-	hex "LPT I/O port"
-	depends on LPT_ENABLE && LPT_IO_PORT_OTHER
-
-config LPT_IO
-	hex
-	depends on LPT_ENABLE
-	default 0x378 if LPT_IO_PORT_378
-	default 0x278 if LPT_IO_PORT_278
-	default LPT_IO_PORT_OTHER_INPUT if LPT_IO_PORT_OTHER
-
-choice
-	prompt "LPT IRQ"
-	default LPT_IRQ_DISABLE
-	depends on LPT_ENABLE
-
-config LPT_IRQ_DISABLE
-	bool "Disable"
-config LPT_IRQ3
-	bool "IRQ3"
-config LPT_IRQ4
-	bool "IRQ4"
-config LPT_IRQ5
-	bool "IRQ5"
-config LPT_IRQ6
-	bool "IRQ6"
-config LPT_IRQ7
-	bool "IRQ7"
-config LPT_IRQ9
-	bool "IRQ9"
-config LPT_IRQ10
-	bool "IRQ10"
-config LPT_IRQ11
-	bool "IRQ11"
-config LPT_IRQ12
-	bool "IRQ12"
-config LPT_IRQ14
-	bool "IRQ14"
-config LPT_IRQ15
-	bool "IRQ15"
-
-endchoice
-
-config LPT_IRQ
-	int
-	depends on LPT_ENABLE
-	default 0 if LPT_IRQ_DISABLE
-	default 3 if LPT_IRQ3
-	default 4 if LPT_IRQ4
-	default 5 if LPT_IRQ5
-	default 6 if LPT_IRQ6
-	default 7 if LPT_IRQ7
-	default 9 if LPT_IRQ9
-	default 10 if LPT_IRQ10
-	default 11 if LPT_IRQ11
-	default 12 if LPT_IRQ12
-	default 14 if LPT_IRQ14
-	default 15 if LPT_IRQ15
-
-choice
-	prompt "LPT Mode Setting"
-	default LPT_MODE_SPP
-	depends on LPT_ENABLE
-
-config LPT_MODE_BPP
-	bool "BPP mode"
-config LPT_MODE_EPP_19_AND_SPP
-	bool "EPP 1.9 and SPP mode"
-config LPT_MODE_ECP
-	bool "ECP Mode"
-config LPT_MODE_ECP_AND_EPP_19
-	bool "ECP and EPP 1.9 mode"
-config LPT_MODE_SPP
-	bool "SPP Mode"
-config LPT_MODE_EPP_17_AND_SPP
-	bool "EPP 1.7 and SPP mode"
-config LPT_MODE_ECP_AND_EPP_17
-	bool "ECP and EPP 1.7 mode"
-
-endchoice
-
-# end of LPT
-
-endmenu
-
-endif # BOARD_DMP_EX
diff --git a/src/mainboard/dmp/vortex86ex/Kconfig.name b/src/mainboard/dmp/vortex86ex/Kconfig.name
deleted file mode 100644
index 8e1a5647d7..0000000000
--- a/src/mainboard/dmp/vortex86ex/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_DMP_EX
-	bool "Vortex86EX"
diff --git a/src/mainboard/dmp/vortex86ex/board_info.txt b/src/mainboard/dmp/vortex86ex/board_info.txt
deleted file mode 100644
index c67b641a94..0000000000
--- a/src/mainboard/dmp/vortex86ex/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: sbc
diff --git a/src/mainboard/dmp/vortex86ex/devicetree.cb b/src/mainboard/dmp/vortex86ex/devicetree.cb
deleted file mode 100644
index 4106bed448..0000000000
--- a/src/mainboard/dmp/vortex86ex/devicetree.cb
+++ /dev/null
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-chip soc/dmp/vortex86ex			# North Bridge
-	device domain 0 on
-		device pci 0.0 on end		# Host Bridge
-		device pci 7.0 on end	# ISA Bridge
-		device pci 8.0 on end	# Ethernet
-		device pci a.0 on end	# USB 1.1
-		device pci a.1 on end	# USB 2.0
-		device pci b.0 on end	# USB 1.1
-		device pci b.1 on end	# USB 2.0
-		device pci c.0 on end	# IDE
-	end # pci domain 0
-	chip cpu/dmp/vortex86ex end	# CPU
-end
diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.c b/src/mainboard/dmp/vortex86ex/hda_verb.c
deleted file mode 100644
index 5c728077da..0000000000
--- a/src/mainboard/dmp/vortex86ex/hda_verb.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
-	/* coreboot specific header */
-	0x10ec0262,     // Codec Vendor / Device ID: Realtek ALC262
-	0x10714700,     // Subsystem ID
-	0x0000000f,     // Number of jacks
-
-	/* ===== HDA Codec Subsystem ID Verb-table ===== */
-	/* HDA Codec Subsystem ID  : 0x10EC0000 */
-	AZALIA_SUBVENDOR(0x0, 0x10ec0000),
-
-	/* ===== Pin Widget Verb-table ===== */
-	/* Widget node 0x01 : */
-	0x0017ff00,
-	0x0017ff00,
-	0x0017ff00,
-	0x0017ff00,
-	/* Pin widget 0x11 - S/PDIF-OUT2 */
-	AZALIA_PIN_CFG(0x0, 0x11, 0x40000000),
-	/* Pin widget 0x12 - DMIC */
-	AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
-	/* Pin widget 0x14 - LINE-OUT (Port-D) */
-	AZALIA_PIN_CFG(0x0, 0x14, 0x01014110),
-	/* Pin widget 0x15 - HP-OUT (Port-A) */
-	AZALIA_PIN_CFG(0x0, 0x15, 0x411111f0),
-	/* Pin widget 0x16 - MONO-OUT */
-	AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),
-	/* Pin widget 0x18 - MIC1 (Port-B) */
-	AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
-	/* Pin widget 0x19 - MIC2 (Port-F) */
-	AZALIA_PIN_CFG(0x0, 0x19, 0x02a19130),
-	/* Pin widget 0x1A - LINE1 (Port-C) */
-	AZALIA_PIN_CFG(0x0, 0x1a, 0x01813140),
-	/* Pin widget 0x1B - LINE2 (Port-E) */
-	AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
-	/* Pin widget 0x1C - CD-IN */
-	AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
-	/* Pin widget 0x1D - BEEP-IN */
-	AZALIA_PIN_CFG(0x0, 0x1d, 0x40354629),
-	/* Pin widget 0x1E - S/PDIF-OUT */
-	AZALIA_PIN_CFG(0x0, 0x1e, 0x18561120),
-	/* Pin widget 0x1F - S/PDIF-IN */
-	AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dmp/vortex86ex/irq_tables.c b/src/mainboard/dmp/vortex86ex/irq_tables.c
deleted file mode 100644
index 9e4e77fd60..0000000000
--- a/src/mainboard/dmp/vortex86ex/irq_tables.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,		/* u32 signature */
-	PIRQ_VERSION,		/* u16 version */
-	32 + 16 * 12,		/* Max. number of devices on the bus */
-	0x00,			/* Interrupt router bus */
-	(0x07 << 3) | 0x0,	/* Interrupt router dev */
-	0,			/* IRQs devoted exclusively to PCI usage */
-	0x17f3,			/* Vendor */
-	0x6031,			/* Device */
-	0,			/* Miniport */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0xa,			/* Checksum (has to be set to some value that
-				 * would give 0 after the sum of all bytes
-				 * for this structure (including checksum).
-				 */
-	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x00, (0x01 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x1, 0x0},
-		{0x00, (0x02 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x2, 0x0},
-		{0x00, (0x03 << 3) | 0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x0, 0x0},
-		{0x00, (0x04 << 3) | 0x0, {{0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}}, 0x4, 0x0},
-		{0x00, (0x05 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x5, 0x0},
-		{0x00, (0x06 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x6, 0x0},
-		{0x00, (0x08 << 3) | 0x0, {{0x05, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x0a << 3) | 0x0, {{0x07, 0xdef8}, {0x08, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x0b << 3) | 0x0, {{0x09, 0xdef8}, {0x0a, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x0c << 3) | 0x0, {{0x0b, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x0f << 3) | 0x0, {{0x0d, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x0e << 3) | 0x0, {{0x0e, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c
deleted file mode 100644
index 108cc1d669..0000000000
--- a/src/mainboard/dmp/vortex86ex/romstage.c
+++ /dev/null
@@ -1,352 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Andrew Wu <arw@dmp.com.tw>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <stdlib.h>
-#include "arch/x86/romcc_console.c"
-#include <console/console.h>
-#include <cpu/x86/cache.h>
-#include <halt.h>
-#include "drivers/pc80/pc/i8254.c"
-#include <soc/dmp/vortex86ex/northbridge.h>
-#include <soc/dmp/vortex86ex/southbridge.h>
-#include "soc/dmp/vortex86ex/raminit.c"
-#include <cpu/dmp/dmp_post_code.h>
-
-#define DMP_CPUID_SX      0x31504d44
-#define DMP_CPUID_DX      0x32504d44
-#define DMP_CPUID_MX      0x33504d44
-#define DMP_CPUID_DX2     0x34504d44
-#define DMP_CPUID_MX_PLUS 0x35504d44
-#define DMP_CPUID_EX      0x37504d44
-
-static u32 get_dmp_id(void)
-{
-	return pci_read_config32(NB, NB_REG_CID);
-}
-
-/* Indirect access registers for Watch-dog timer, GPIO PORT 0,1
- * Index port is for I/O port 22h
- * Index port 13h (00: lock register, C5h: unlock register) for lock/unlock function
- * Index port 37h, 39h, 3Ah, 3Bh, 3Ch for Watchdog timer
- * Index port 46h, 47h, 4Ch, 4Dh, 4Eh, 4Fh for GPIO port 0, 1
- */
-static void write_indirect_reg(u8 index, u8 data)
-{
-	outb(index, 0x22);
-	outb(data, 0x23);
-}
-
-static void lock_indirect_reg(void)
-{
-	write_indirect_reg(0x13, 0x00);
-}
-
-static void unlock_indirect_reg(void)
-{
-	write_indirect_reg(0x13, 0xc5);
-}
-
-static void disable_watchdog(void)
-{
-	unlock_indirect_reg();
-	// disable watchdog timer
-	write_indirect_reg(0x37, 0x0);
-}
-
-void set_ex_powerdown_control(void)
-{
-	u32 powerdown_ctrl;
-	powerdown_ctrl = pci_read_config32(SB, 0xbc);
-#if IS_ENABLED(CONFIG_TEMP_POWERDOWN)
-	powerdown_ctrl |= (1 << 31);
-#endif
-#if IS_ENABLED(CONFIG_SATA_POWERDOWN)
-	powerdown_ctrl |= (1 << 30);
-#endif
-#if IS_ENABLED(CONFIG_ADC_POWERDOWN)
-	powerdown_ctrl |= (1 << 28);
-#endif
-#if IS_ENABLED(CONFIG_PCIE0_POWERDOWN)
-	powerdown_ctrl |= (1 << 13);
-#endif
-#if IS_ENABLED(CONFIG_MAC_POWERDOWN)
-	powerdown_ctrl |= (1 << 3);
-#endif
-#if IS_ENABLED(CONFIG_USB1_POWERDOWN)
-	powerdown_ctrl |= (1 << 1);
-#endif
-#if IS_ENABLED(CONFIG_IDE_POWERDOWN)
-	powerdown_ctrl |= (1 << 0);
-#endif
-	pci_write_config32(SB, 0xbc, powerdown_ctrl);
-}
-
-static void set_pci_nb_pmcr(void)
-{
-	u8 pmcr = pci_read_config8(NB, NB_REG_PMCR);
-	/*
-	 * Set PCI Master Max Cycle Length (MCL) to 32 PCI clocks.
-	 * Set PCI Master Burst Write Length (BL) to Burst length over 3.
-	 */
-	pmcr |= 0x0f;
-	pci_write_config8(NB, NB_REG_PMCR, pmcr);
-}
-
-static void set_pci_sb_lpccr(void)
-{
-	u8 lpccr = pci_read_config8(SB, SB_REG_LPCCR);
-	/* Set PCI Soft Reset Control to 1.
-	 * (When the CPU soft reset is initialized, PCIRST# will be active.)
-	 * Set P92FE to 1. (I/O port 92 Register Write Function Enable.)
-	 * Set P92S to 1. (Internal Port 92h Selected.)
-	 */
-	lpccr |= 0x16;
-	pci_write_config8(SB, SB_REG_LPCCR, lpccr);
-	/* enable fast ga20 */
-	outb(inb(SYSTEM_CTL_PORT) | 0x02, SYSTEM_CTL_PORT);
-}
-
-static u32 make_uart_config(u16 base, u8 irq)
-{
-	/* Set base IO address only, skip IRQ. IRQ will be setup in
-	 * southbridge stage. */
-	u32 cfg = 0;
-	cfg |= 1 << 23;		// UE = enabled.
-	cfg |= base;		// UIOA.
-	return cfg;
-}
-
-#define SETUP_UART(n) \
-	uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\
-	outl(uart_cfg, 0xc00 + (n - 1) * 4);
-
-static void ex_uart_early_init(void)
-{
-#if CONFIG_TTYS0_BASE
-	u32 uart_cfg = 0;
-	/* Set UART Config I/O base address to 0xc00 */
-	pci_write_config16(SB, 0x60, 0xc01);
-	/* If serial console base address is defined, find out which
-	 * UART uses this address, and setup this UART first. */
-#if CONFIG_TTYS0_BASE == CONFIG_UART1_IO
-	SETUP_UART(1)
-#elif CONFIG_TTYS0_BASE == CONFIG_UART2_IO
-	SETUP_UART(2)
-#elif CONFIG_TTYS0_BASE == CONFIG_UART3_IO
-	SETUP_UART(3)
-#elif CONFIG_TTYS0_BASE == CONFIG_UART4_IO
-	SETUP_UART(4)
-#elif CONFIG_TTYS0_BASE == CONFIG_UART5_IO
-	SETUP_UART(5)
-#elif CONFIG_TTYS0_BASE == CONFIG_UART6_IO
-	SETUP_UART(6)
-#elif CONFIG_TTYS0_BASE == CONFIG_UART7_IO
-	SETUP_UART(7)
-#elif CONFIG_TTYS0_BASE == CONFIG_UART8_IO
-	SETUP_UART(8)
-#elif CONFIG_TTYS0_BASE == CONFIG_UART9_IO
-	SETUP_UART(9)
-#elif CONFIG_TTYS0_BASE == CONFIG_UART10_IO
-	SETUP_UART(10)
-#endif
-#endif
-}
-
-static void init_wdt1(void)
-{
-#if IS_ENABLED(CONFIG_WDT1_INITIALIZE)
-#if IS_ENABLED(CONFIG_WDT1_ENABLE)
-	outb(0x1 << 6, 0xa8);
-#endif
-	u8 wdt1_signal_reg = 0;
-#if IS_ENABLED(CONFIG_WDT1_SINGAL_NMI)
-	wdt1_signal_reg = 0x0c << 4;
-#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_RESET)
-	wdt1_signal_reg = 0x0d << 4;
-#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_SMI)
-	wdt1_signal_reg = 0x0e << 4;
-#endif
-	outb(wdt1_signal_reg, 0xa9);
-#endif
-}
-
-/* Fill 32bit pattern into specified DRAM region. */
-static void fill_dram(u32 * p, u32 pattern, u32 test_len)
-{
-	if (test_len == 0)
-		return;
-#if 0
-	// C version, very slow.
-	for (p = (u32 *) 0; (u32) p < test_len; p++) {
-		*p = pattern;
-	}
-#endif
-	// ASM version, much faster.
-	asm volatile (
-		"cld\n\t"
-		"rep\n\t"
-		"stosl"
-		: /* no output registers */
-		: "c" (test_len / 4), "a" (pattern), "D" (p)
-	);
-}
-
-/* Verify 32bit pattern in specified DRAM region.
- * Return -1 if ok, failed memory address if error. */
-static int verify_dram(u32 * p, u32 pattern, u32 test_len)
-{
-	if (test_len == 0)
-		return -1;
-#if 0
-	// C version, very slow.
-	for (p = (u32 *) 0; (u32) p < test_len; p++) {
-		if (*p != pattern) {
-			return (int)p;
-		}
-	}
-	return -1;
-#endif
-	u16 flags;
-	int addr;
-	asm volatile (
-		"cld\n\t"
-		"rep\n\t"
-		"scasl\n\t"
-		"lahf\n\t"
-		: "=a" (flags), "=D" (addr)
-		: "c" (test_len / 4), "a" (pattern), "D" (p)
-	);
-	if (flags & (1 << (6 + 8)))	// x86 zero flag = bit 6.
-	{
-		return -1;	// verify ok
-	}
-	return addr - 4;	// verify error, return error address.
-}
-
-static void test_dram_stability(void)
-{
-	u32 test_len = 2048 * 1024;
-	u32 pat = 0x5aa5a55a;
-	u32 ext_mem_start = 0xc0000;
-	u32 base_mem_test_len = test_len > 640 * 1024 ? 640 * 1024 : test_len;
-	u32 ext_mem_test_len = test_len > ext_mem_start ? test_len - ext_mem_start : 0;
-	if (ext_mem_test_len > 0) {
-		/* Enable all shadow RAM region C0000 - FFFFF. */
-		pci_write_config32(NB, NB_REG_MAR, 0x3ffffff0);
-	}
-	int v;
-	fill_dram((u32 *) 0, pat, base_mem_test_len);
-	fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
-	v = verify_dram((u32 *) 0, pat, base_mem_test_len);
-	if (v == -1) {
-		v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
-	}
-	/* Change pattern and test again */
-	if (v == -1) {
-		pat = 0xa55a5aa5;
-		fill_dram((u32 *) 0, pat, base_mem_test_len);
-		fill_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
-		v = verify_dram((u32 *) 0, pat, base_mem_test_len);
-		if (v == -1) {
-			v = verify_dram((u32 *) ext_mem_start, pat, ext_mem_test_len);
-		}
-	}
-	if (v != -1) {
-		post_code(POST_DMP_DRAM_TEST_ERR);
-		print_emerg("DRAM stablility test error!\nADDR = ");
-		print_emerg_hex32(v);
-		print_emerg(", WRITE = ");
-		print_emerg_hex32(pat);
-		u32 r = *(u32 *) v;
-		print_emerg(", READ = ");
-		print_emerg_hex32(r);
-		print_emerg(", XOR = ");
-		print_emerg_hex32(r ^ pat);
-		print_emerg("\n");
-		die("System halted.\n");
-	}
-	if (ext_mem_test_len > 0) {
-		/* Disable shadow RAM. */
-		pci_write_config32(NB, NB_REG_MAR, 0x0);
-	}
-}
-
-static void enable_l2_cache(void)
-{
-	/*
-	 * Enable L2 cache by setting PCI N/B function 1 L2 cache
-	 * control register (0xe8) bit 0 (L2_EN) and bit 1 (L2_WB_EN).
-	 */
-	u32 reg_nb_f1_e8;
-	reg_nb_f1_e8 = pci_read_config8(NB1, 0xe8);
-	reg_nb_f1_e8 |= 3;
-	pci_write_config8(NB1, 0xe8, reg_nb_f1_e8);
-}
-
-static void main(unsigned long bist)
-{
-	u32 dmp_id;
-
-	dmp_id = get_dmp_id();
-	if (dmp_id != DMP_CPUID_EX) {
-		/* Not DMP Vortex86EX CPU. */
-		post_code(POST_DMP_ID_ERR);
-		halt();
-	}
-	disable_watchdog();
-	set_ex_powerdown_control();
-	set_pci_nb_pmcr();
-	set_pci_sb_lpccr();
-	ex_uart_early_init();
-
-	console_init();
-
-	init_wdt1();
-
-	/* Initialize i8254 timers */
-	post_code(0x42);
-	setup_i8254();
-
-	/* Initialize DRAM */
-	u8 reg_nb_f1_cc;
-	/* Setup DDR3 Timing reg 0-3 / Config reg */
-	pci_write_config16(NB, 0x6e, 0x0a2f);
-	pci_write_config32(NB, 0x74, 0x84010200);
-	pci_write_config32(NB, 0x78, 0x33405544);
-	pci_write_config32(NB, 0x7c, 0x2e0f0e0b);
-	/* Disable enhance read push write */
-	reg_nb_f1_cc = pci_read_config8(NB1, 0xcc);
-	reg_nb_f1_cc &= ~(1 << 4);
-	pci_write_config8(NB1, 0xcc, reg_nb_f1_cc);
-	if (detect_ddr3_dram_size()) {
-		post_code(POST_DMP_DRAM_SIZING_ERR);
-		die("DRAM sizing error!\n");
-	}
-	/* Reset enhance read push write to default(enable) */
-	reg_nb_f1_cc |= (1 << 4);
-	pci_write_config8(NB1, 0xcc, reg_nb_f1_cc);
-
-	print_ddr3_memory_setup();
-	test_dram_stability();
-
-	/* CPU setup, romcc pukes on invd() */
-	asm volatile ("invd");
-	enable_cache();
-
-	enable_l2_cache();
-}
diff --git a/src/soc/dmp/vortex86ex/Kconfig b/src/soc/dmp/vortex86ex/Kconfig
deleted file mode 100644
index 7c616d6f29..0000000000
--- a/src/soc/dmp/vortex86ex/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-config SOC_DMP_VORTEX86EX
-	bool
-	select LATE_CBMEM_INIT
-	select AZALIA_PLUGIN_SUPPORT
-	select HAVE_HARD_RESET
diff --git a/src/soc/dmp/vortex86ex/Makefile.inc b/src/soc/dmp/vortex86ex/Makefile.inc
deleted file mode 100644
index a896fcd6fc..0000000000
--- a/src/soc/dmp/vortex86ex/Makefile.inc
+++ /dev/null
@@ -1,26 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ifeq ($(CONFIG_SOC_DMP_VORTEX86EX),y)
-
-ramstage-y += northbridge.c
-ramstage-y += xgi_oprom.c
-
-ramstage-y += southbridge.c
-ramstage-y += hard_reset.c
-ramstage-y += ide_sd_sata.c
-ramstage-y += audio.c
-
-endif
diff --git a/src/soc/dmp/vortex86ex/audio.c b/src/soc/dmp/vortex86ex/audio.c
deleted file mode 100644
index 05a0d8c7d2..0000000000
--- a/src/soc/dmp/vortex86ex/audio.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/azalia_device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-/* RDC HD audio controller */
-static const struct pci_driver rdc_audio __pci_driver = {
-	.ops	= &default_azalia_audio_ops,
-	.vendor	= PCI_VENDOR_ID_RDC,
-	.device	= 0x3010,
-};
diff --git a/src/soc/dmp/vortex86ex/chip.h b/src/soc/dmp/vortex86ex/chip.h
deleted file mode 100644
index d67b8014c1..0000000000
--- a/src/soc/dmp/vortex86ex/chip.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_DMP_VORTEX86EX
-#define _SOC_DMP_VORTEX86EX
-
-struct soc_dmp_vortex86ex_config {
-	/* PCI function enables */
-	/* i.e. so that pci scan bus will find them. */
-	/* I am putting in IDE as an example but obviously this needs
-	 * to be more complete!
-	 */
-	int enable_ide;
-	/* enables of functions of devices */
-	int enable_usb;
-	int enable_native_ide;
-	int enable_com_ports;
-	int enable_keyboard;
-	int enable_nvram;
-};
-
-#endif				/* _SOC_DMP_VORTEX86EX */
diff --git a/src/soc/dmp/vortex86ex/hard_reset.c b/src/soc/dmp/vortex86ex/hard_reset.c
deleted file mode 100644
index fe127aab91..0000000000
--- a/src/soc/dmp/vortex86ex/hard_reset.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_hard_reset(void)
-{
-}
diff --git a/src/soc/dmp/vortex86ex/ide_sd_sata.c b/src/soc/dmp/vortex86ex/ide_sd_sata.c
deleted file mode 100644
index c60018ab49..0000000000
--- a/src/soc/dmp/vortex86ex/ide_sd_sata.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-#include <stdlib.h>
-#include <string.h>
-#include <arch/io.h>
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-
-/* Vortex86EX IDE to SD/STAT controller need to enable ATA decoder and
- * setup timing. */
-
-/*
- * Primary ATA Timing Register (PATR) - Offset 40-41h
- * Secondary ATA Timing Register (PATR) - Offset 42-43h
- *
- * Bit     R/W     Default Description
- * 15      R/W     0h      ATA Decode Enable. Decode the I/O addressing ranges assigned to this controller.
- *                         1: Enabled.
- *                         0: Disabled.
- * 14      R/W     0b      Device 1 ATA Timing Register Enable
- *                         1: Enable the device 1 ATA timing.
- *                         0: Disable the device 1 ATA timing
- * 13-12   R/W     0h      IORDY Sample Mode. Sets the setup time before IORDY are sampled.
- *                         00: PIO-0
- *                         10: PIO-2, SW-2
- *                         10: PIO-3, PIO-4, MW-1, MW-2
- *                         11: Reserved
- * 11-10   RO      0h      Reserved
- * 9-8     R/W     0h      Recovery Mode. Sets the hold time after IORDY are sampled.
- *                         00: PIO-0, PIO-2, SW-2
- *                         10: PIO-3, MW-1
- *                         10: Reserved
- *                         11: PIO-4, MW-2
- * 7       R/W     0b      DMA Timing Enable Only Select 1
- *                         1: Enable the device timings for DMA operation for device 1
- *                         0: Disable the device timings for DMA operation for device 1
- * 6       R/W     0b      ATA/ATAPI Device Indicator 1
- *                         1: Indicate presence od an ATA device
- *                         0: Indicate presence od an ATAPI device
- * 5       R/W     0b      IORDY Sample Point Enabled Select 1
- *                         1: Enable IORDY sample for PIO transfers for device 1
- *                         0: Disable IORDY sample for PIO transfers for device 1
- * 4       R/W     0b      Fast Drive Timing Select 1
- *                         1: Enable faster than PIO-0 timing modes for device 1
- *                         0: Disable faster than PIO-0 timing modes for device 1
- * 3       R/W     0b      DMA Timing Enable Only Select 0
- *                         1: Enable the device timings for DMA operation for device 0
- *                         0: Disable the device timings for DMA operation for device 0
- * 2       R/W     0b      ATA/ATAPI Device Indicator 0
- *                         1: Indicate presence od an ATA device
- *                         0: Indicate presence od an ATAPI device
- * 1       R/W     0b      IORDY Sample Point Enabled Select 0
- *                         1: Enable IORDY sample for PIO transfers for device 0
- *                         0: Disable IORDY sample for PIO transfers for device 0
- * 0       R/W     0b      Fast Drive Timing Select 0
- *                         1: Enable faster than PIO-0 timing modes for device 0
- *                         0: Disable faster than PIO-0 timing modes for device 0
- * */
-
-static void init_ide_ata_timing(struct device *dev)
-{
-	u16 ata_timing_pri, ata_timing_sec;
-	u32 ata_timing_reg32;
-	/* Primary channel is SD. */
-#if IS_ENABLED(CONFIG_IDE1_ENABLE)
-	ata_timing_pri = 0x8000;
-#else
-	ata_timing_pri = 0x0000;	// Disable this channel.
-#endif
-	/* Secondary channel is SATA. */
-#if IS_ENABLED(CONFIG_IDE2_ENABLE)
-	ata_timing_sec = 0xa30f;	// This setting value works well.
-#else
-	ata_timing_sec = 0x0000;	// Disable this channel.
-#endif
-	ata_timing_reg32 = (ata_timing_sec << 16) | ata_timing_pri;
-	pci_write_config32(dev, 0x40, ata_timing_reg32);
-#if IS_ENABLED(CONFIG_IDE_NATIVE_MODE)
-	/* Set both IDE channels to native mode. */
-	u8 prog_if;
-	prog_if = pci_read_config8(dev, 0x09);
-	prog_if |= 5;
-	pci_write_config8(dev, 0x09, prog_if);
-#endif
-	/* MMC function enable. */
-	u32 sd_ctrl_reg;
-	sd_ctrl_reg = pci_read_config32(dev, 0x94);
-	sd_ctrl_reg |= 0x0200;
-	pci_write_config32(dev, 0x94, sd_ctrl_reg);
-	printk(BIOS_INFO, "Vortex86EX IDE controller ATA TIMING reg = %08x\n", ata_timing_reg32);
-}
-
-static void setup_std_ide_compatible(struct device *dev)
-{
-#if IS_ENABLED(CONFIG_IDE_STANDARD_COMPATIBLE)
-	// Misc Control Register (MCR) Offset 90h
-	// bit 0 = Vendor ID Access, bit 1 = Device ID Access.
-	u8 mcr;
-	u16 vendor = (u16) (CONFIG_IDE_COMPATIBLE_SELECTION >> 16);
-	u16 device = (u16) (CONFIG_IDE_COMPATIBLE_SELECTION & 0xffff);
-	// unlock vendor/device ID access bits.
-	mcr = pci_read_config8(dev, 0x90);
-	pci_write_config8(dev, 0x90, mcr | 3);
-	pci_write_config16(dev, 0x00, vendor);
-	pci_write_config16(dev, 0x02, device);
-	// restore lock bits.
-	pci_write_config8(dev, 0x90, mcr);
-#endif
-}
-
-static void vortex_ide_init(struct device *dev)
-{
-	if (dev->device == 0x1010) {
-		// This is SX/old DX IDE controller.
-		// Set IOCFG bit 15/13 : IDE Decoder Enable for Primary/Secondary channel.
-		u16 iocfg = 0xa000;
-		pci_write_config16(dev, 0x40, iocfg);
-	} else if (dev->device == 0x1011 || dev->device == 0x1012) {
-		// This is new DX/MX/MX+/DX2 IDE controller.
-		init_ide_ata_timing(dev);
-		setup_std_ide_compatible(dev);
-	}
-}
-
-static struct device_operations vortex_ide_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = vortex_ide_init,
-	.scan_bus         = 0,
-};
-
-static const struct pci_driver vortex_ide_driver_1010 __pci_driver = {
-	.ops    = &vortex_ide_ops,
-	.vendor = PCI_VENDOR_ID_RDC,
-	.device = 0x1010,
-};
-
-static const struct pci_driver vortex_ide_driver_1011 __pci_driver = {
-	.ops    = &vortex_ide_ops,
-	.vendor = PCI_VENDOR_ID_RDC,
-	.device = 0x1011,
-};
-
-static const struct pci_driver vortex_ide_driver_1012 __pci_driver = {
-	.ops    = &vortex_ide_ops,
-	.vendor = PCI_VENDOR_ID_RDC,
-	.device = 0x1012,
-};
diff --git a/src/soc/dmp/vortex86ex/northbridge.c b/src/soc/dmp/vortex86ex/northbridge.c
deleted file mode 100644
index d811ba92e5..0000000000
--- a/src/soc/dmp/vortex86ex/northbridge.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cbmem.h>
-#include <pc80/mc146818rtc.h>
-#include "chip.h"
-#include "northbridge.h"
-
-#define SPI_BASE 0xfc00
-
-static void northbridge_init(device_t dev)
-{
-	printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n");
-	// enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable.
-	pci_write_config32(dev, NB_REG_MAR, 0x3ff000f0);
-	// enable C0000h - C3FFFh/C4000h - C7FFF can be in L1 cache selection.
-	pci_write_config32(dev, NB_REG_HOST_CTL, (1 << 18) | (1 << 19));
-	// Set SPI register base.
-	pci_write_config16(dev, NB_REG_SPI_BASE, SPI_BASE | 1);
-}
-
-static struct device_operations northbridge_operations = {
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = northbridge_init
-};
-
-static const struct pci_driver northbridge_driver_6025 __pci_driver = {
-	.ops = &northbridge_operations,
-	.vendor = PCI_VENDOR_ID_RDC,
-	.device = 0x6025,	/* EX CPU N/B ID */
-};
-
-/* Set CMOS register 15h/16h/17h/18h for base/extended
- * memory size. */
-static void set_cmos_memory_size(unsigned long sizek)
-{
-	unsigned long ext_mem_size;
-	u8 ext_mem_size_hb, ext_mem_size_lb;
-	/* calculate memory size between 1M - 65M. */
-	ext_mem_size = sizek - 1024;
-	if (ext_mem_size > 65535)
-		ext_mem_size = 65535;
-	ext_mem_size_hb = (u8) (ext_mem_size >> 8);
-	ext_mem_size_lb = (u8) (ext_mem_size & 0xff);
-	/* Base memory is always 640K. */
-	cmos_write(0x80, 0x15);
-	cmos_write(0x02, 0x16);
-	/* Write extended memory size. */
-	cmos_write(ext_mem_size_lb, 0x17);
-	cmos_write(ext_mem_size_hb, 0x18);
-	/* register 0x30(48) is RTC_BOOT_BYTE for coreboot,
-	 * don't touch it. */
-}
-
-static void pci_domain_set_resources(device_t dev)
-{
-	device_t mc_dev;
-	uint32_t pci_tolm;
-
-	printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n");
-
-	pci_tolm = find_pci_tolm(dev->link_list);
-	mc_dev = dev->link_list->children;
-	if (mc_dev) {
-		unsigned long tomk, tolmk;
-		int idx;
-		int ss;
-		/* Get DDRII size setting from northbridge register. */
-		/* SS = 0 for 2MB, 1 for 4MB, 2 for 8MB, 3 for 16MB ... */
-		ss = pci_read_config16(mc_dev, 0x6c);
-		ss = ((ss >> 8) & 0xf);
-		tomk = (2 * 1024) << ss;
-		printk(BIOS_DEBUG, "I would set RAM size to %ld Mbytes\n", (tomk >> 10));
-		/* Compute the top of Low memory */
-		tolmk = pci_tolm >> 10;
-		if (tolmk >= tomk)
-			/* The PCI hole does does not overlap the memory.
-			 */
-			tolmk = tomk;
-
-		set_late_cbmem_top(tolmk * 1024);
-
-		/* Report the memory regions */
-		idx = 10;
-		ram_resource(dev, idx++, 0, 640);	/* first 640k */
-		ram_resource(dev, idx++, 768, tolmk - 768);	/* leave a hole for vga */
-		set_cmos_memory_size(tolmk);
-	}
-	assign_resources(dev->link_list);
-}
-
-static struct device_operations pci_domain_ops = {
-	.read_resources   = pci_domain_read_resources,
-	.set_resources    = pci_domain_set_resources,
-	.enable_resources = NULL,
-	.init             = NULL,
-	.scan_bus         = pci_domain_scan_bus,
-	.ops_pci_bus      = pci_bus_default_ops,
-};
-
-static void enable_dev(struct device *dev)
-{
-	printk(BIOS_SPEW, "In vortex86ex enable_dev for device %s.\n", dev_path(dev));
-
-	/* Set the operations if it is a special bus type */
-	if (dev->path.type == DEVICE_PATH_DOMAIN) {
-		dev->ops = &pci_domain_ops;
-	}
-}
-
-struct chip_operations northbridge_dmp_vortex86ex_ops = {
-	CHIP_NAME("DMP Vortex86EX Northbridge")
-	.enable_dev = enable_dev,
-};
diff --git a/src/soc/dmp/vortex86ex/northbridge.h b/src/soc/dmp/vortex86ex/northbridge.h
deleted file mode 100644
index d5bb6f1c3a..0000000000
--- a/src/soc/dmp/vortex86ex/northbridge.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef NORTHBRIDGE_H
-#define NORTHBRIDGE_H
-
-#define	NB			PCI_DEV(0, 0, 0)
-#define	NB_REG_SPI_BASE		0x40
-#define	NB_REG_CLK_OUT_CTL	0x48
-#define	NB_REG_PCI_CLK_CTL	0x4b
-#define	NB_REG_STRAP		0x60
-#define	NB_REG_STRAP2		0x64
-#define	NB_REG_MBR		0x6c
-#define	NB_REG_DDR3_CFG		0x74
-#define	NB_REG_DDR3_MTR1	0x78
-#define	NB_REG_DDR3_MTR2	0x7c
-#define	NB_REG_SMM		0x83
-#define	NB_REG_MAR		0x84
-#define	NB_REG_CID		0x90
-#define	NB_REG_S1R		0x94
-#define	NB_REG_S2R		0x98
-#define	NB_REG_S3R		0x9c
-#define	NB_REG_HOST_CTL		0xa0
-#define	NB_REG_CPU_MBCR		0xc4
-#define	NB_REG_CDR		0xd0
-#define	NB_REG_PACR		0xf0
-#define	NB_REG_PMCR		0xf4
-#define	NB_REG_PCI_TARGET	0xf8
-#define	NB_REG_PCSCR		0xfc
-
-/* Additional "virtual" device, just extension of NB */
-#define NB1			PCI_DEV(0, 0, 1)
-#define NB1_REG_FJZ_PHY_CTL1	0x80
-#define NB1_REG_FJZ_PHY_CTL2	0x84
-#define NB1_REG_FJZ_PHY_CTL3	0x88
-#define NB1_REG_FJZ_DRAM_CTL1	0x90
-#define NB1_REG_FJZ_DRAM_CTL2	0x94
-#define NB1_REG_FJZ_DRAM_CTL3	0x98
-#define NB1_REG_FJZ_DRAM_CTL4	0x9c
-#define NB1_REG_PLL_TEST_CTL	0xa8
-#define NB1_REG_DDR3_PWR_SAV	0xbc
-#define NB1_REG_DDR3_CTL_OPT1	0xc0
-#define NB1_REG_DDR3_CTL_OPT3	0xc8
-#define NB1_REG_DDR3_CTL_OPT4	0xcc
-#define NB1_REG_DDR3_CTL_OPT5	0xce
-#define NB1_REG_PLL_TEST_MODE	0xd0
-#define NB1_REG_L2_CACHE_CTL	0xe8
-#define NB1_REG_SSCR		0xec
-#define NB1_REG_NB_CTL_OPT1	0xf4
-#define NB1_REG_UPDATE_PHY_IO	0xf8
-#define NB1_REG_RESET_DRAMC_PHY	0xfa
-
-#endif				/* NORTHBRIDGE_H */
diff --git a/src/soc/dmp/vortex86ex/raminit.c b/src/soc/dmp/vortex86ex/raminit.c
deleted file mode 100644
index 0d4b5b56b3..0000000000
--- a/src/soc/dmp/vortex86ex/raminit.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-static u16 get_mask(u16 bit_width, u16 bit_offset)
-{
-	u16 mask = (((1 << bit_width) - 1) << bit_offset);
-	return mask;
-}
-
-static u16 set_bitfield(u16 val, u16 bits, u16 bit_width, u16 bit_offset)
-{
-	u16 mask = get_mask(bit_width, bit_offset);
-	val = (val & ~mask) | (bits << bit_offset);
-	return val;
-}
-
-static u16 get_bitfield(u16 val, u16 bit_width, u16 bit_offset)
-{
-	u16 mask = get_mask(bit_width, bit_offset);
-	return (val & mask) >> bit_offset;
-}
-
-static u8 check_address_bit(int addr_bit)
-{
-	u16 dummy;
-	*(volatile u16 *)(0) = 0;
-	dummy = *(volatile u16 *)(0);	// read push write
-	*(volatile u16 *)(1 << addr_bit) = 0x5a5a;
-	dummy = *(volatile u16 *)(1 << addr_bit);	// read push write
-	if ((*(volatile u16 *)(0)) != 0)
-		return 0;	// address bit wrapped.
-	return 1;		// address bit not wrapped.
-}
-
-static u8 check_dram_side(int addr_bit)
-{
-	*(volatile u16 *)(1 << addr_bit) = 0x5a5a;
-	*(volatile u16 *)(0) = 0;
-	if ((*(volatile u16 *)(1 << addr_bit)) != 0x5a5a)
-		return 0;	// DRAM only one side.
-	return 1;		// two sides.
-}
-
-// DDRIII memory bank register control:
-// bit    :
-// 2 - 0  : DRAMC_COLSIZE : DDRIII Column Address Type : 0 0 0 = 10bit
-//                                                     : 0 0 1 = 11bit
-// 7 - 5  : DRAMC_ROWSIZE : DDRIII Row Address Type    : 0 0 0 = 13bit
-//                                                     : 0 0 1 = 14bit
-//                                                     : 0 1 0 = 15bit
-//                                                     : 0 1 1 = 16bit
-// 11 - 8 : DRAM_SIZE     : DDRIII Size                : 0 1 0 1 =  64M
-//                                                     : 0 1 1 0 = 128M
-//                                                     : 0 1 1 1 = 256M
-//                                                     : 1 0 0 0 = 512M
-//                                                     : 1 0 0 1 = 1GB
-//                                                     : 1 0 1 0 = 2GB
-// 13     : DRAMC_CSMASK  : DDRIII CS#[1] Mask         : 1 = Mask CS1 enable
-
-#define DDR3_COL_10BIT  0
-#define DDR3_COL_11BIT  1
-#define DDR3_ROW_13BIT  0
-#define DDR3_ROW_14BIT  1
-#define DDR3_ROW_15BIT  2
-#define DDR3_ROW_16BIT  3
-#define DDR3_SIZE_64M   5
-#define DDR3_SIZE_128M  6
-#define DDR3_SIZE_256M  7
-#define DDR3_SIZE_512M  8
-#define DDR3_SIZE_1GB   9
-#define DDR3_SIZE_2GB   10
-#define DDR3_C1M_ACTIVE 0
-#define DDR3_C1M_MASK   1
-
-static u16 set_ddr3_mem_reg_col(u16 reg, u16 col)
-{
-	return set_bitfield(reg, col, 3, 0);
-}
-
-static u16 get_ddr3_mem_reg_col(u16 reg)
-{
-	return get_bitfield(reg, 3, 0);
-}
-
-static u16 set_ddr3_mem_reg_row(u16 reg, u16 row)
-{
-	return set_bitfield(reg, row, 3, 5);
-}
-
-static u16 get_ddr3_mem_reg_row(u16 reg)
-{
-	return get_bitfield(reg, 3, 5);
-}
-
-static u16 set_ddr3_mem_reg_size(u16 reg, u16 size)
-{
-	return set_bitfield(reg, size, 4, 8);
-}
-
-static u16 get_ddr3_mem_reg_size(u16 reg)
-{
-	return get_bitfield(reg, 4, 8);
-}
-
-static u16 set_ddr3_mem_reg_c1m(u16 reg, u16 c1m)
-{
-	return set_bitfield(reg, c1m, 1, 13);
-}
-
-static u16 get_ddr3_mem_reg_c1m(u16 reg)
-{
-	return get_bitfield(reg, 1, 13);
-}
-
-static u16 auto_set_ddr3_mem_reg_size(u16 reg)
-{
-	u8 ss = 0;
-	// If reg is the minimum DRAM size,
-	// SS is also the minimum size 128M.
-	// If size in reg is bigger, SS is also bigger.
-	ss += get_ddr3_mem_reg_col(reg);
-	ss += get_ddr3_mem_reg_row(reg);
-	ss += (1 - get_ddr3_mem_reg_c1m(reg));
-	ss += DDR3_SIZE_128M;
-	return set_ddr3_mem_reg_size(reg, ss);
-}
-
-static u16 get_ddr3_mem_reg(u16 col, u16 row, u16 c1m)
-{
-	u16 reg;
-	reg = 0;
-	reg = set_ddr3_mem_reg_col(reg, col);
-	reg = set_ddr3_mem_reg_row(reg, row);
-	reg = set_ddr3_mem_reg_c1m(reg, c1m);
-	reg = auto_set_ddr3_mem_reg_size(reg);
-	return reg;
-}
-
-static void ddr3_phy_reset(void)
-{
-	// PCI N/B reg FAh bit 6 = RST_DRAM_PHY.
-	pci_write_config8(NB1, NB1_REG_RESET_DRAMC_PHY, 0x40);
-	while ((pci_read_config8(NB1, NB1_REG_RESET_DRAMC_PHY) & 0x40) == 0x40) {
-	}
-	// reload mode.
-	u32 ddr3_cfg = pci_read_config32(NB, NB_REG_DDR3_CFG);
-	pci_write_config32(NB, NB_REG_DDR3_CFG, ddr3_cfg);
-}
-
-static u8 detect_ddr3_dram_cs(u16 reg, u8 base_addr_bit)
-{
-	reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_ACTIVE);
-	reg = auto_set_ddr3_mem_reg_size(reg);
-	pci_write_config16(NB, NB_REG_MBR, reg);
-	if (check_dram_side(base_addr_bit + 1)) {
-		base_addr_bit += 1;
-		return 0;
-	}
-
-	reg = set_ddr3_mem_reg_c1m(reg, DDR3_C1M_MASK);
-	reg = auto_set_ddr3_mem_reg_size(reg);
-	pci_write_config16(NB, NB_REG_MBR, reg);
-	// no need to check CS = 0.
-	// Need to reset DDR3 PHY.
-	ddr3_phy_reset();
-	return 0;
-}
-
-static u8 detect_ddr3_dram_row(u16 reg, u8 base_addr_bit)
-{
-	reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_16BIT);
-	reg = auto_set_ddr3_mem_reg_size(reg);
-	pci_write_config16(NB, NB_REG_MBR, reg);
-	if (check_address_bit(base_addr_bit + 16)) {
-		base_addr_bit += 16;
-		return detect_ddr3_dram_cs(reg, base_addr_bit);
-	}
-
-	reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_15BIT);
-	reg = auto_set_ddr3_mem_reg_size(reg);
-	pci_write_config16(NB, NB_REG_MBR, reg);
-	if (check_address_bit(base_addr_bit + 15)) {
-		base_addr_bit += 15;
-		return detect_ddr3_dram_cs(reg, base_addr_bit);
-	}
-
-	reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_14BIT);
-	reg = auto_set_ddr3_mem_reg_size(reg);
-	pci_write_config16(NB, NB_REG_MBR, reg);
-	if (check_address_bit(base_addr_bit + 14)) {
-		base_addr_bit += 14;
-		return detect_ddr3_dram_cs(reg, base_addr_bit);
-	}
-
-	reg = set_ddr3_mem_reg_row(reg, DDR3_ROW_13BIT);
-	reg = auto_set_ddr3_mem_reg_size(reg);
-	pci_write_config16(NB, NB_REG_MBR, reg);
-	if (check_address_bit(base_addr_bit + 13)) {
-		base_addr_bit += 13;
-		return detect_ddr3_dram_cs(reg, base_addr_bit);
-	}
-	// row test error.
-	return 1;
-}
-
-static u8 detect_ddr3_dram_bank(u16 reg, u8 base_addr_bit)
-{
-	/* DDR3 is always 3 bank bits */
-	base_addr_bit += 3;
-	return detect_ddr3_dram_row(reg, base_addr_bit);
-}
-
-static u8 detect_ddr3_dram_col(u16 reg, u8 base_addr_bit)
-{
-	reg = set_ddr3_mem_reg_col(reg, DDR3_COL_11BIT);
-	reg = auto_set_ddr3_mem_reg_size(reg);
-	pci_write_config16(NB, NB_REG_MBR, reg);
-	if (check_address_bit(base_addr_bit + 11)) {
-		base_addr_bit += 11;
-		return detect_ddr3_dram_bank(reg, base_addr_bit);
-	}
-
-	reg = set_ddr3_mem_reg_col(reg, DDR3_COL_10BIT);
-	reg = auto_set_ddr3_mem_reg_size(reg);
-	pci_write_config16(NB, NB_REG_MBR, reg);
-	if (check_address_bit(base_addr_bit + 10)) {
-		base_addr_bit += 10;
-		return detect_ddr3_dram_bank(reg, base_addr_bit);
-	}
-	// col test error.
-	return 1;
-}
-
-static u8 detect_ddr3_dram_size(void)
-{
-	u16 reg;
-	u8 base_addr_bit = 0;
-	reg = get_ddr3_mem_reg(DDR3_COL_10BIT, DDR3_ROW_13BIT, DDR3_C1M_MASK);
-	return detect_ddr3_dram_col(reg, base_addr_bit);
-}
-
-static void print_ddr3_memory_setup(void)
-{
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
-	printk(BIOS_DEBUG, "DDR3 Timing Reg 0-3:\n");
-	printk(BIOS_DEBUG, "NB 6e : ");
-	print_debug_hex16(pci_read_config16(NB, 0x6e));
-	printk(BIOS_DEBUG, "\nNB 74 : ");
-	print_debug_hex32(pci_read_config32(NB, 0x74));
-	printk(BIOS_DEBUG, "\nNB 78 : ");
-	print_debug_hex32(pci_read_config32(NB, 0x78));
-	printk(BIOS_DEBUG, "\nNB 7c : ");
-	print_debug_hex32(pci_read_config32(NB, 0x7c));
-	u16 mbr = pci_read_config16(NB, 0x6c);
-	printk(BIOS_DEBUG, "\nNB 6c(MBR) : ");
-	print_debug_hex16(mbr);
-	const char *s;
-	u8 col = get_ddr3_mem_reg_col(mbr);
-	if (col == DDR3_COL_10BIT)
-		s = " (COL=10";
-	else
-		s = " (COL=11";
-	print_debug(s);
-	u8 row = get_ddr3_mem_reg_row(mbr);
-	switch (row) {
-	case DDR3_ROW_13BIT:
-		s = ", ROW = 13";
-		break;
-	case DDR3_ROW_14BIT:
-		s = ", ROW = 14";
-		break;
-	case DDR3_ROW_15BIT:
-		s = ", ROW = 15";
-		break;
-	default:
-		s = ", ROW = 16";
-		break;
-	}
-	print_debug(s);
-	u8 size = get_ddr3_mem_reg_size(mbr);
-	switch (size) {
-	case DDR3_SIZE_64M:
-		s = ", 64M";
-		break;
-	case DDR3_SIZE_128M:
-		s = ", 128M";
-		break;
-	case DDR3_SIZE_256M:
-		s = ", 256M";
-		break;
-	case DDR3_SIZE_512M:
-		s = ", 512M";
-		break;
-	case DDR3_SIZE_1GB:
-		s = ", 1GB";
-		break;
-	case DDR3_SIZE_2GB:
-		s = ", 2GB";
-		break;
-	}
-	print_debug(s);
-	u8 mask = get_ddr3_mem_reg_c1m(mbr);
-	if (mask == DDR3_C1M_ACTIVE)
-		s = ", CS MASK Enable)\n";
-	else
-		s = ", CS Mask Disable)\n";
-	print_debug(s);
-#endif
-}
diff --git a/src/soc/dmp/vortex86ex/southbridge.c b/src/soc/dmp/vortex86ex/southbridge.c
deleted file mode 100644
index 1d3c897103..0000000000
--- a/src/soc/dmp/vortex86ex/southbridge.c
+++ /dev/null
@@ -1,632 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/keyboard.h>
-#include <string.h>
-#include <delay.h>
-#include "arch/io.h"
-#include "chip.h"
-#include "southbridge.h"
-#include "cpu/dmp/dmp_post_code.h"
-
-/* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */
-static const unsigned char irq_to_int_routing[16] = {
-	0x0, 0x0, 0x0, 0x2,	// IRQ0-2 is unmappable, IRQ3 = 2.
-	0x4, 0x5, 0x7, 0x6,	// IRQ4-7 = 4, 5, 7, 6.
-	0x0, 0x1, 0x3, 0x9,	// IRQ8 is unmappable, IRQ9-11 = 1, 3, 9.
-	0xb, 0x0, 0xd, 0xf	// IRQ12 = b, IRQ13 is unmappable, IRQ14-15 = d, f.
-};
-
-/* S/B PCI Interrupt routing table reg(0x58) field bit shift. */
-#define EHCIH_IRQ_SHIFT 28
-#define OHCII_IRQ_SHIFT 24
-#define MAC_IRQ_SHIFT 16
-#define RT3_IRQ_SHIFT 12
-#define RT2_IRQ_SHIFT 8
-#define RT1_IRQ_SHIFT 4
-#define RT0_IRQ_SHIFT 0
-
-/* S/B Extend PCI Interrupt routing table reg(0xb4) field bit shift. */
-#define CAN_IRQ_SHIFT 28
-#define HDA_IRQ_SHIFT 20
-#define USBD_IRQ_SHIFT 16
-#define SIDE_IRQ_SHIFT 12
-#define PIDE_IRQ_SHIFT 8
-
-/* S/B function 1 Extend PCI Interrupt routing table reg 2(0xb4)
- * field bit shift.
- */
-#define SPI1_IRQ_SHIFT 8
-#define MOTOR_IRQ_SHIFT 0
-
-/* in-chip PCI device IRQs(0 for disabled). */
-#define EHCII_IRQ 5
-#define OHCII_IRQ 5
-#define MAC_IRQ 6
-
-#define CAN_IRQ 10
-#define HDA_IRQ 7
-#define USBD_IRQ 6
-#define PIDE_IRQ 5
-
-#define SPI1_IRQ 10
-#define I2C0_IRQ 10
-#define MOTOR_IRQ 11
-
-/* RT0-3 IRQs. */
-#define RT3_IRQ 3
-#define RT2_IRQ 4
-#define RT1_IRQ 5
-#define RT0_IRQ 6
-
-/* IDE legacy mode IRQs. */
-#define IDE1_LEGACY_IRQ 14
-#define IDE2_LEGACY_IRQ 15
-
-/* Internal parallel port */
-#define LPT_INT_C 0
-#define LPT_INT_ACK_SET 0
-#define LPT_UE 1
-#define LPT_PDMAS 0
-#define LPT_DREQS 0
-
-/* keyboard controller system flag timeout : 400 ms */
-#define KBC_TIMEOUT_SYS_FLAG 400
-
-static u8 get_pci_dev_func(device_t dev)
-{
-	return PCI_FUNC(dev->path.pci.devfn);
-}
-
-static void verify_dmp_keyboard_error(void)
-{
-	post_code(POST_DMP_KBD_FW_VERIFY_ERR);
-	die("Internal keyboard firmware verify error!\n");
-}
-
-static void upload_dmp_keyboard_firmware(struct device *dev)
-{
-	u32 reg_sb_c0;
-	u32 fwptr;
-
-	// enable firmware uploading function by set bit 10.
-	post_code(POST_DMP_KBD_FW_UPLOAD);
-	reg_sb_c0 = pci_read_config32(dev, SB_REG_IPFCR);
-	pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 | 0x400);
-
-	outw(0, 0x62);		// reset upload address to 0.
-	// upload 4096 bytes from 0xFFFFE000.
-	outsb(0x66, (u8 *) 0xffffe000, 4096);
-	// upload 4096 bytes from 0xFFFFC000.
-	outsb(0x66, (u8 *) 0xffffc000, 4096);
-
-	outw(0, 0x62);		// reset upload address to 0.
-	// verify 4096 bytes from 0xFFFFE000.
-	for (fwptr = 0xffffe000; fwptr < 0xfffff000; fwptr++) {
-		if (inb(0x66) != *(u8 *) fwptr) {
-			verify_dmp_keyboard_error();
-		}
-	}
-	// verify 4096 bytes from 0xFFFFC000.
-	for (fwptr = 0xffffc000; fwptr < 0xffffd000; fwptr++) {
-		if (inb(0x66) != *(u8 *) fwptr) {
-			verify_dmp_keyboard_error();
-		}
-	}
-
-	// disable firmware uploading.
-	pci_write_config32(dev, SB_REG_IPFCR, reg_sb_c0 & ~0x400L);
-}
-
-static int kbc_wait_system_flag(void)
-{
-	/* wait keyboard controller ready by checking system flag
-	 * (status port bit 2).
-	 */
-	post_code(POST_DMP_KBD_CHK_READY);
-	u32 timeout;
-	for (timeout = KBC_TIMEOUT_SYS_FLAG;
-	     timeout && ((inb(0x64) & 0x4) == 0); timeout--)
-		mdelay(1);
-
-	if (!timeout) {
-		printk(BIOS_WARNING, "Keyboard controller system flag timeout\n");
-	}
-	return !!timeout;
-}
-
-static void pci_routing_fixup(struct device *dev)
-{
-	const unsigned slot[3] = { 0 };
-	const unsigned char slot_irqs[1][4] = {
-		{RT0_IRQ, RT1_IRQ, RT2_IRQ, RT3_IRQ},
-	};
-	const int slot_num = 1;
-	int i;
-	u32 int_routing = 0;
-	u32 ext_int_routing = 0;
-
-	/* assign PCI-e bridge (bus#0, dev#1, fn#0) IRQ to RT0. */
-	pci_assign_irqs(0, 1, slot_irqs[0]);
-
-	/* RT0 is enabled. */
-	int_routing |= irq_to_int_routing[RT0_IRQ] << RT0_IRQ_SHIFT;
-
-	/* assign PCI slot IRQs. */
-	for (i = 0; i < slot_num; i++) {
-		pci_assign_irqs(1, slot[i], slot_irqs[i]);
-	}
-
-	/* Read PCI slot IRQs to see if RT1-3 is used, and enables it */
-	for (i = 0; i < slot_num; i++) {
-		unsigned int funct;
-		device_t pdev;
-		u8 irq;
-
-		/* Each slot may contain up to eight functions. */
-		for (funct = 0; funct < 8; funct++) {
-			pdev = dev_find_slot(1, (slot[i] << 3) + funct);
-			if (!pdev)
-				continue;
-			irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
-			if (irq == RT1_IRQ) {
-				int_routing |= irq_to_int_routing[RT1_IRQ] << RT1_IRQ_SHIFT;
-			} else if (irq == RT2_IRQ) {
-				int_routing |= irq_to_int_routing[RT2_IRQ] << RT2_IRQ_SHIFT;
-			} else if (irq == RT3_IRQ) {
-				int_routing |= irq_to_int_routing[RT3_IRQ] << RT3_IRQ_SHIFT;
-			}
-		}
-	}
-
-	/* Setup S/B PCI Interrupt routing table reg(0x58). */
-	int_routing |= irq_to_int_routing[EHCII_IRQ] << EHCIH_IRQ_SHIFT;
-	int_routing |= irq_to_int_routing[OHCII_IRQ] << OHCII_IRQ_SHIFT;
-	int_routing |= irq_to_int_routing[MAC_IRQ] << MAC_IRQ_SHIFT;
-	pci_write_config32(dev, SB_REG_PIRQ_ROUTE, int_routing);
-
-	/* Setup S/B PCI Extend Interrupt routing table reg(0xb4). */
-	ext_int_routing |= irq_to_int_routing[CAN_IRQ] << CAN_IRQ_SHIFT;
-	ext_int_routing |= irq_to_int_routing[HDA_IRQ] << HDA_IRQ_SHIFT;
-	ext_int_routing |= irq_to_int_routing[USBD_IRQ] << USBD_IRQ_SHIFT;
-#if IS_ENABLED(CONFIG_IDE_NATIVE_MODE)
-	/* IDE in native mode, only uses one IRQ. */
-	ext_int_routing |= irq_to_int_routing[0] << SIDE_IRQ_SHIFT;
-	ext_int_routing |= irq_to_int_routing[PIDE_IRQ] << PIDE_IRQ_SHIFT;
-#else
-	/* IDE in legacy mode, use IRQ 14, 15. */
-	ext_int_routing |= irq_to_int_routing[IDE2_LEGACY_IRQ] << SIDE_IRQ_SHIFT;
-	ext_int_routing |= irq_to_int_routing[IDE1_LEGACY_IRQ] << PIDE_IRQ_SHIFT;
-#endif
-	pci_write_config32(dev, SB_REG_EXT_PIRQ_ROUTE, ext_int_routing);
-
-	/* Assign in-chip PCI device IRQs. */
-	if (MAC_IRQ) {
-		unsigned char irqs[4] = { MAC_IRQ, 0, 0, 0 };
-		pci_assign_irqs(0, 0x8, irqs);
-	}
-	if ((OHCII_IRQ != 0) && (EHCII_IRQ != 0)) {
-		unsigned char irqs[4] = { OHCII_IRQ, EHCII_IRQ, 0, 0 };
-		pci_assign_irqs(0, 0xa, irqs);
-	}
-	if ((CONFIG_IDE_NATIVE_MODE != 0) && (PIDE_IRQ != 0)) {
-		/* IDE in native mode, setup PCI IRQ. */
-		unsigned char irqs[4] = { PIDE_IRQ, 0, 0, 0 };
-		pci_assign_irqs(0, 0xc, irqs);
-	}
-	if (CAN_IRQ) {
-		unsigned char irqs[4] = { CAN_IRQ, 0, 0, 0 };
-		pci_assign_irqs(0, 0x11, irqs);
-	}
-	if (HDA_IRQ) {
-		unsigned char irqs[4] = { HDA_IRQ, 0, 0, 0 };
-		pci_assign_irqs(0, 0xe, irqs);
-	}
-	if (USBD_IRQ) {
-		unsigned char irqs[4] = { USBD_IRQ, 0, 0, 0 };
-		pci_assign_irqs(0, 0xf, irqs);
-	}
-}
-
-static void vortex_sb_init(struct device *dev)
-{
-	u32 lpt_reg = 0;
-
-#if IS_ENABLED(CONFIG_LPT_ENABLE)
-	int ppmod = 0;
-#if IS_ENABLED(CONFIG_LPT_MODE_BPP)
-	ppmod = 0;
-#elif IS_ENABLED(CONFIG_LPT_MODE_EPP_19_AND_SPP)
-	ppmod = 1;
-#elif IS_ENABLED(CONFIG_LPT_MODE_ECP)
-	ppmod = 2;
-#elif IS_ENABLED(CONFIG_LPT_MODE_ECP_AND_EPP_19)
-	ppmod = 3;
-#elif IS_ENABLED(CONFIG_LPT_MODE_SPP)
-	ppmod = 4;
-#elif IS_ENABLED(CONFIG_LPT_MODE_EPP_17_AND_SPP)
-	ppmod = 5;
-#elif IS_ENABLED(CONFIG_LPT_MODE_ECP_AND_EPP_17)
-	ppmod = 7;
-#else
-#error CONFIG_LPT_MODE error.
-#endif
-
-	/* Setup internal parallel port */
-	lpt_reg |= (LPT_INT_C << 28);
-	lpt_reg |= (LPT_INT_ACK_SET << 27);
-	lpt_reg |= (ppmod << 24);
-	lpt_reg |= (LPT_UE << 23);
-	lpt_reg |= (LPT_PDMAS << 22);
-	lpt_reg |= (LPT_DREQS << 20);
-	lpt_reg |= (irq_to_int_routing[CONFIG_LPT_IRQ] << 16);
-	lpt_reg |= (CONFIG_LPT_IO << 0);
-#endif				// CONFIG_LPT_ENABLE
-	pci_write_config32(dev, SB_REG_IPPCR, lpt_reg);
-}
-
-#define SETUP_GPIO_ADDR(n) \
-	u32 cfg##n = (CONFIG_GPIO_P##n##_DIR_ADDR << 16) | (CONFIG_GPIO_P##n##_DATA_ADDR);\
-	outl(cfg##n, base + 4 + (n * 4));\
-	gpio_enable_mask |= (1 << n);
-
-#define INIT_GPIO(n) \
-	outb(CONFIG_GPIO_P##n##_INIT_DIR, CONFIG_GPIO_P##n##_DIR_ADDR);\
-	outb(CONFIG_GPIO_P##n##_INIT_DATA, CONFIG_GPIO_P##n##_DATA_ADDR);
-
-static void ex_sb_gpio_init(struct device *dev)
-{
-	const int base = 0xb00;
-	u32 gpio_enable_mask = 0;
-	/* S/B register 63h - 62h : GPIO Port Config IO Base Address */
-	pci_write_config16(dev, SB_REG_GPIO_CFG_IO_BASE, base | 1);
-	/* Set GPIO port 0~9 base address.
-	 * Config Base + 04h, 08h, 0ch... : GPIO port 0~9 data/dir decode addr.
-	 * Bit 31-16 : DBA, GPIO direction base address.
-	 * Bit 15-0  : DPBA, GPIO data port base address.
-	 * */
-#if IS_ENABLED(CONFIG_GPIO_P0_ENABLE)
-	SETUP_GPIO_ADDR(0)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P1_ENABLE)
-	SETUP_GPIO_ADDR(1)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P2_ENABLE)
-	SETUP_GPIO_ADDR(2)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P3_ENABLE)
-	SETUP_GPIO_ADDR(3)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P4_ENABLE)
-	SETUP_GPIO_ADDR(4)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P5_ENABLE)
-	SETUP_GPIO_ADDR(5)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P6_ENABLE)
-	SETUP_GPIO_ADDR(6)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P7_ENABLE)
-	SETUP_GPIO_ADDR(7)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P8_ENABLE)
-	SETUP_GPIO_ADDR(8)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P9_ENABLE)
-	SETUP_GPIO_ADDR(9)
-#endif
-	/* Enable GPIO port 0~9. */
-	outl(gpio_enable_mask, base);
-	/* Set GPIO port 0-9 initial dir and data. */
-#if IS_ENABLED(CONFIG_GPIO_P0_ENABLE)
-	INIT_GPIO(0)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P1_ENABLE)
-	INIT_GPIO(1)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P2_ENABLE)
-	INIT_GPIO(2)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P3_ENABLE)
-	INIT_GPIO(3)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P4_ENABLE)
-	INIT_GPIO(4)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P5_ENABLE)
-	INIT_GPIO(5)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P6_ENABLE)
-	INIT_GPIO(6)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P7_ENABLE)
-	INIT_GPIO(7)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P8_ENABLE)
-	INIT_GPIO(8)
-#endif
-#if IS_ENABLED(CONFIG_GPIO_P9_ENABLE)
-	INIT_GPIO(9)
-#endif
-	/* Disable GPIO Port Config IO Base Address. */
-	pci_write_config16(dev, SB_REG_GPIO_CFG_IO_BASE, 0x0);
-}
-
-static u32 make_uart_config(u16 base, u8 irq)
-{
-	u8 mapped_irq = irq_to_int_routing[irq];
-	u32 cfg = 0;
-	cfg |= 1 << 23;			// UE = enabled.
-	cfg |= (mapped_irq << 16);	// UIRT.
-	cfg |= base;			// UIOA.
-	return cfg;
-}
-
-#define SETUP_UART(n) \
-	uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\
-	outl(uart_cfg, base + (n - 1) * 4);
-
-static void ex_sb_uart_init(struct device *dev)
-{
-	const int base = 0xc00;
-	u32 uart_cfg = 0;
-	/* S/B register 61h - 60h : UART Config IO Base Address */
-	pci_write_config16(dev, SB_REG_UART_CFG_IO_BASE, base | 1);
-	/* setup UART */
-#if IS_ENABLED(CONFIG_UART1_ENABLE)
-	SETUP_UART(1)
-#endif
-#if IS_ENABLED(CONFIG_UART2_ENABLE)
-	SETUP_UART(2)
-#endif
-#if IS_ENABLED(CONFIG_UART3_ENABLE)
-	SETUP_UART(3)
-#endif
-#if IS_ENABLED(CONFIG_UART4_ENABLE)
-	SETUP_UART(4)
-#endif
-#if IS_ENABLED(CONFIG_UART5_ENABLE)
-	SETUP_UART(5)
-#endif
-#if IS_ENABLED(CONFIG_UART6_ENABLE)
-	SETUP_UART(6)
-#endif
-#if IS_ENABLED(CONFIG_UART7_ENABLE)
-	SETUP_UART(7)
-#endif
-#if IS_ENABLED(CONFIG_UART8_ENABLE)
-	SETUP_UART(8)
-#endif
-#if IS_ENABLED(CONFIG_UART9_ENABLE)
-	SETUP_UART(9)
-#endif
-#if IS_ENABLED(CONFIG_UART10_ENABLE)
-	SETUP_UART(10)
-#endif
-	/* Keep UART Config I/O base address */
-	//pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0);
-}
-
-static void i2c_init(struct device *dev)
-{
-	u8 mapped_irq = irq_to_int_routing[I2C0_IRQ];
-	u32 cfg = 0;
-	cfg |= 1 << 31;			// UE = enabled.
-	cfg |= (mapped_irq << 16);	// IIRT0.
-	cfg |= CONFIG_I2C_BASE;		// UIOA.
-	pci_write_config32(dev, SB_REG_II2CCR, cfg);
-}
-
-static int get_rtc_update_in_progress(void)
-{
-	if (cmos_read(RTC_REG_A) & RTC_UIP)
-		return 1;
-	return 0;
-}
-
-static void unsafe_read_cmos_rtc(u8 rtc[7])
-{
-	rtc[0] = cmos_read(RTC_CLK_ALTCENTURY);
-	rtc[1] = cmos_read(RTC_CLK_YEAR);
-	rtc[2] = cmos_read(RTC_CLK_MONTH);
-	rtc[3] = cmos_read(RTC_CLK_DAYOFMONTH);
-	rtc[4] = cmos_read(RTC_CLK_HOUR);
-	rtc[5] = cmos_read(RTC_CLK_MINUTE);
-	rtc[6] = cmos_read(RTC_CLK_SECOND);
-}
-
-static void read_cmos_rtc(u8 rtc[7])
-{
-	/* Read RTC twice and check update-in-progress flag, to make
-	 * sure RTC is correct */
-	u8 rtc_new[7];
-	while (get_rtc_update_in_progress()) ;
-	unsafe_read_cmos_rtc(rtc_new);
-	do {
-		memcpy(rtc, rtc_new, 7);
-		while (get_rtc_update_in_progress()) ;
-		unsafe_read_cmos_rtc(rtc_new);
-	} while (memcmp(rtc_new, rtc, 7) != 0);
-}
-
-/*
- * Convert a number in decimal format into the BCD format.
- * Return 255 if not a valid BCD value.
- */
-static u8 bcd2dec(u8 bcd)
-{
-	u8 h, l;
-	h = bcd >> 4;
-	l = bcd & 0xf;
-	if (h > 9 || l > 9)
-		return 255;
-	return h * 10 + l;
-}
-
-static void fix_cmos_rtc_time(void)
-{
-	/* Read RTC data. */
-	u8 rtc[7];
-	read_cmos_rtc(rtc);
-
-	/* Convert RTC from BCD format to binary. */
-	u8 bin_rtc[7];
-	int i;
-	for (i = 0; i < 7; i++) {
-		bin_rtc[i] = bcd2dec(rtc[i]);
-	}
-
-	/* If RTC date is invalid, fix it. */
-	if (bin_rtc[0] > 99 || bin_rtc[1] > 99 || bin_rtc[2] > 12 || bin_rtc[3] > 31) {
-		/* Set PC compatible timing mode. */
-		cmos_write(0x26, RTC_REG_A);
-		cmos_write(0x02, RTC_REG_B);
-		/* Now setup a default date 2008/08/08 08:08:08. */
-		cmos_write(0x8, RTC_CLK_SECOND);
-		cmos_write(0x8, RTC_CLK_MINUTE);
-		cmos_write(0x8, RTC_CLK_HOUR);
-		cmos_write(0x6, RTC_CLK_DAYOFWEEK);	/* Friday */
-		cmos_write(0x8, RTC_CLK_DAYOFMONTH);
-		cmos_write(0x8, RTC_CLK_MONTH);
-		cmos_write(0x8, RTC_CLK_YEAR);
-		cmos_write(0x20, RTC_CLK_ALTCENTURY);
-	}
-}
-
-static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size)
-{
-	struct resource *res;
-	res = new_resource(dev, index);
-	res->base = base;
-	res->size = size;
-	res->limit = 0xffffUL;
-	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size)
-{
-	/* SPI flash is in topmost of 4G memory space */
-	struct resource *res;
-	res = new_resource(dev, index);
-	res->base = 0x100000000LL - flash_size;
-	res->size = flash_size;
-	res->limit = 0xffffffffUL;
-	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
-static void vortex86_sb_read_resources(device_t dev)
-{
-	u32 flash_size = 8 * 1024 * 1024;
-
-	pci_dev_read_resources(dev);
-
-	if (dev->device == 0x6011) {
-		/* It is EX CPU southbridge */
-		if (get_pci_dev_func(dev) != 0) {
-			/* only for function 0, skip function 1 */
-			return;
-		}
-		/* default SPI flash ROM is 64MB */
-		flash_size = 64 * 1024 * 1024;
-	}
-
-	/* Reserve space for legacy I/O */
-	vortex86_sb_set_io_resv(dev, 1, 0, 0x1000UL);
-
-	/* Reserve space for flash */
-	vortex86_sb_set_spi_flash_size(dev, 2, flash_size);
-
-	/* Reserve space for I2C */
-	vortex86_sb_set_io_resv(dev, 3, CONFIG_I2C_BASE, 8);
-}
-
-static void southbridge_init_func1(struct device *dev)
-{
-	/* Handle S/B function 1 PCI IRQ routing. (SPI1/MOTOR) */
-	u32 ext_int_routing2 = 0;
-	/* Setup S/B function 1 PCI Extend Interrupt routing table reg 2(0xb4). */
-	ext_int_routing2 |= irq_to_int_routing[SPI1_IRQ] << SPI1_IRQ_SHIFT;
-	ext_int_routing2 |= irq_to_int_routing[MOTOR_IRQ] << MOTOR_IRQ_SHIFT;
-	pci_write_config32(dev, SB1_REG_EXT_PIRQ_ROUTE2, ext_int_routing2);
-
-	/* Assign in-chip PCI device IRQs. */
-	if ((SPI1_IRQ != 0) || (MOTOR_IRQ != 0)) {
-		unsigned char irqs[4] = { MOTOR_IRQ, SPI1_IRQ, 0, 0 };
-		pci_assign_irqs(0, 0x10, irqs);
-	}
-}
-
-static void southbridge_init(struct device *dev)
-{
-	/* Check it is function 0 or 1. (Same Vendor/Device ID) */
-	if (get_pci_dev_func(dev) != 0) {
-		southbridge_init_func1(dev);
-		return;
-	}
-	upload_dmp_keyboard_firmware(dev);
-	vortex_sb_init(dev);
-	if (dev->device == 0x6011) {
-		ex_sb_gpio_init(dev);
-		ex_sb_uart_init(dev);
-		i2c_init(dev);
-	}
-	pci_routing_fixup(dev);
-
-	fix_cmos_rtc_time();
-	cmos_init(0);
-	/* Check keyboard controller ready. If timeout, reload firmware code
-	 * and try again.
-	 */
-	u32 retries = 10;
-	while (!kbc_wait_system_flag()) {
-		if (!retries) {
-			post_code(POST_DMP_KBD_IS_BAD);
-			die("The keyboard timeout occurred too often. "
-			    "Your CPU is probably defect. "
-			    "Contact your dealer to replace it\n");
-		}
-		upload_dmp_keyboard_firmware(dev);
-		retries--;
-	}
-	post_code(POST_DMP_KBD_IS_READY);
-	pc_keyboard_init(NO_AUX_DEVICE);
-}
-
-static struct device_operations vortex_sb_ops = {
-	.read_resources   = vortex86_sb_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = &southbridge_init,
-	.scan_bus         = scan_lpc_bus,
-	.enable           = 0,
-	.ops_pci          = 0,
-};
-
-static const struct pci_driver pci_driver_6011 __pci_driver = {
-	.ops    = &vortex_sb_ops,
-	.vendor = PCI_VENDOR_ID_RDC,
-	.device = 0x6011,	/* EX CPU S/B ID */
-};
-
-struct chip_operations southbridge_dmp_vortex86ex_ops = {
-	CHIP_NAME("DMP Vortex86EX Southbridge")
-	.enable_dev = 0
-};
diff --git a/src/soc/dmp/vortex86ex/southbridge.h b/src/soc/dmp/vortex86ex/southbridge.h
deleted file mode 100644
index c2b91027ae..0000000000
--- a/src/soc/dmp/vortex86ex/southbridge.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef SOUTHBRIDGE_H
-#define SOUTHBRIDGE_H
-
-#define	SB			PCI_DEV(0, 7, 0)
-#define	SB_REG_LPCCR		0x41
-#define	SB_REG_FRCSCR		0x42
-#define	SB_REG_PIRQ_ROUTE	0x58
-#define	SB_REG_UART_CFG_IO_BASE	0x60
-#define	SB_REG_GPIO_CFG_IO_BASE	0x62
-#define	SB_REG_CS_BASE0		0x90
-#define	SB_REG_CS_BASE_MASK0	0x94
-#define	SB_REG_CS_BASE1		0x98
-#define	SB_REG_CS_BASE_MASK1	0x9c
-#define	SB_REG_IPPCR		0xb0
-#define	SB_REG_EXT_PIRQ_ROUTE	0xb4
-#define	SB_REG_OCDCR		0xbc
-#define	SB_REG_IPFCR		0xc0
-#define	SB_REG_FRWPR		0xc4
-#define	SB_REG_STRAP		0xce
-#define	SB_REG_II2CCR		0xd4
-
-#define	SB1			PCI_DEV(0, 7, 1)
-#define	SB1_REG_EXT_PIRQ_ROUTE2	0xb4
-
-#define	SYSTEM_CTL_PORT         0x92
-
-#endif				/* SOUTHBRIDGE_H */
diff --git a/src/soc/dmp/vortex86ex/xgi_oprom.c b/src/soc/dmp/vortex86ex/xgi_oprom.c
deleted file mode 100644
index b72157d37f..0000000000
--- a/src/soc/dmp/vortex86ex/xgi_oprom.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/********************************************************************
- * Change the vendor / device IDs to match the XGI Z9S VBIOS header.
- ********************************************************************/
-#include <device/pci.h>
-u32 map_oprom_vendev(u32 vendev)
-{
-	u32 new_vendev = vendev;
-
-	switch (vendev) {
-	case 0x18ca0020:
-		new_vendev = 0x18ca0021;
-		break;
-	}
-
-	return new_vendev;
-}