diff options
| author | V Sowmya <v.sowmya@intel.com> | 2017-07-12 14:27:09 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-15 23:11:16 +0000 |
| commit | 752dc8e4258b708dc4a96b3d929163b1560492ae (patch) | |
| tree | 35778030113a6f0936c7774ef4e6520050e25917 | |
| parent | 1e6b980b1ec49e5ffdfb34e5373f13e82db67fb7 (diff) | |
| download | coreboot-752dc8e4258b708dc4a96b3d929163b1560492ae.tar.xz | |
soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros
Rename BAR0 and BAR2 SRAM base and size macros to align with the spec.
* PMC_SRAM_BASE_0 -> SRAM_BASE_0
* PMC_SRAM_SIZE_0 -> SRAM_SIZE_0
* PMC_SRAM_BASE_1 -> SRAM_BASE_2
* PMC_SRAM_SIZE_1 -> SRAM_SIZE_2
Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20539
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/apollolake/acpi/pmc_ipc.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/iomap.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/sram.c | 10 |
3 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index 33c829e656..5c53af4cd9 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -52,7 +52,7 @@ scope (\_SB) { Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA) CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) - Store (PMC_SRAM_BASE_0, SBAS) + Store (SRAM_BASE_0, SBAS) Return (^RBUF) } diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index a8e4bc9bc5..c3eb66bef6 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -39,10 +39,10 @@ #define PMC_BAR1 0xfe044000 #define PMC_BAR0_SIZE (8 * KiB) -#define PMC_SRAM_BASE_0 0xfe900000 -#define PMC_SRAM_SIZE_0 (8 * KiB) -#define PMC_SRAM_BASE_1 0xfe902000 -#define PMC_SRAM_SIZE_1 (4 * KiB) +#define SRAM_BASE_0 0xfe900000 +#define SRAM_SIZE_0 (8 * KiB) +#define SRAM_BASE_2 0xfe902000 +#define SRAM_SIZE_2 (4 * KiB) /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 diff --git a/src/soc/intel/apollolake/sram.c b/src/soc/intel/apollolake/sram.c index 0225327550..70e1330549 100644 --- a/src/soc/intel/apollolake/sram.c +++ b/src/soc/intel/apollolake/sram.c @@ -26,13 +26,13 @@ static void read_resources(device_t dev) pci_dev_read_resources(dev); res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = PMC_SRAM_BASE_0; - res->size = PMC_SRAM_SIZE_0; + res->base = SRAM_BASE_0; + res->size = SRAM_SIZE_0; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, PCI_BASE_ADDRESS_2); - res->base = PMC_SRAM_BASE_1; - res->size = PMC_SRAM_SIZE_1; + res->base = SRAM_BASE_2; + res->size = SRAM_SIZE_2; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } @@ -51,7 +51,7 @@ static void set_resources(device_t dev) pci_write_config32(dev, res->index, res->base); dev->command |= PCI_COMMAND_MEMORY; res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, " SRAM BAR 1"); + report_resource_stored(dev, res, " SRAM BAR 2"); } static const struct device_operations device_ops = { |