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authorAndrey Petrov <andrey.petrov@intel.com>2016-06-24 18:15:09 -0700
committerMartin Roth <martinroth@google.com>2016-08-28 18:35:03 +0200
commit7f72c9b30ec543fc5d485dca5f15790d2c4b03f3 (patch)
treecc5cf99611f05bcfb5dc2d9d39ff17ea2ccfb4f1
parent0dde2917a5056bc57cf6da9b2fc41723701b6d41 (diff)
downloadcoreboot-7f72c9b30ec543fc5d485dca5f15790d2c4b03f3.tar.xz
soc/intel/apollolake: Update stage link addresses for 768 KiB cache
Update link addresses for romstage and verstage. Also update FSP-M relocation address. BUG=chrome-os-partner:51959 Change-Id: Ia51a341f05b33151ea5fda9f8620408b5a15bc19 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15454 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/apollolake/Kconfig6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index a92a05281d..d8e33caf7b 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -145,13 +145,13 @@ config X86_TOP4G_BOOTMEDIA_MAP
config ROMSTAGE_ADDR
hex
- default 0xfef3e000
+ default 0xfef20000
help
The base address (in CAR) where romstage should be linked
config VERSTAGE_ADDR
hex
- default 0xfef60000
+ default 0xfef40000
help
The base address (in CAR) where verstage should be linked
@@ -161,7 +161,7 @@ config CACHE_MRC_SETTINGS
config FSP_M_ADDR
hex
- default 0xfef60000
+ default 0xfef40000
help
The address FSP-M will be relocated to during build time