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| author | Tobias Diedrich <ranma+openocd@tdiedrich.de> | 2017-11-25 22:25:16 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-07 02:36:18 +0000 |
| commit | 85dc0d8daedc496435bba8c4c2a740b70f97ae9c (patch) | |
| tree | dcc155d9d4c816730bc31f30f1e63117552c7b22 | |
| parent | 7b093e46270b0fc0f4f0318b2af4ffde42c64cdb (diff) | |
| download | coreboot-85dc0d8daedc496435bba8c4c2a740b70f97ae9c.tar.xz | |
intel/bd82x6x: Fix a small mistake in DIR_ROUTE
The register is 16-bits wide. If the DIR_ROUTE call ordering was
reversed the previous writes would get overwritten.
See page 407ff on the Intel C216 datasheet, which says
"Size: 16bits" with "Default: 3210h" for all DnnIR registers.
This also makes sense given the register offsets:
3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W
[3142h would be D30IR]
3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W
3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W
3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W
314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W
3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W
[discontinuity in register addresses here]
315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W
[315Eh would be D21IR]
3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W
Change-Id: I970abbacbc2c59e86c1726171272b8779758e53e
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 51f3b94239..83d9d8d1dd 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -418,7 +418,7 @@ int rtc_failure(void); #define SOFT_RESET_DATA 0x38f8 #define DIR_ROUTE(x,a,b,c,d) \ - RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ + RCBA16(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ ((b) << DIR_IBR) | ((a) << DIR_IAR)) #define RC 0x3400 /* 32bit */ |