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authorStefan Reinauer <reinauer@chromium.org>2012-06-28 12:22:28 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-07-26 21:42:38 +0200
commit8730bf8aad995bf105454ac1a93dee4c7b5565d5 (patch)
tree220ba909d23366df20cc793a0a898f09e1f7672f
parent7dc2864be7fcc342bab0c167997803f5faf147a1 (diff)
downloadcoreboot-8730bf8aad995bf105454ac1a93dee4c7b5565d5.tar.xz
bd82x6x: Use CMOS variable if available for power-on on power failure
We used a hard coded value for some reason. Don't do that, but use CMOS instead. Modelled after http://review.coreboot.org/#/c/443 to get bd82x6x in sync. Change-Id: I36d715310157b9f9074f2a1c80710f85833020b4 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1324 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/southbridge/intel/bd82x6x/smihandler.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 29f1a1e9ad..da5b52b413 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -29,6 +29,7 @@
#include <device/pci_def.h>
#include <cpu/x86/smm.h>
#include <elog.h>
+#include <pc80/mc146818rtc.h>
#include "pch.h"
#include "nvs.h"
@@ -324,11 +325,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
u8 reg8;
u32 reg32;
u8 slp_typ;
- /* FIXME: the power state on boot should be read from
- * CMOS or even better from GNVS. Right now it's hard
- * coded at compile time.
- */
u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+
+ // save and recover RTC port values
+ u8 tmp70, tmp72;
+ tmp70 = inb(0x70);
+ tmp72 = inb(0x72);
+ get_option(&s5pwr, "power_on_after_fail");
+ outb(tmp70, 0x70);
+ outb(tmp72, 0x72);
+
void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep;
/* First, disable further SMIs */