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| author | Patrick Havelange <patrick.havelange@essensium.com> | 2019-06-18 12:15:07 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-06-25 16:09:05 +0000 |
| commit | 88164787ee7e7d9e13d5a9b95093fd70394ddc46 (patch) | |
| tree | 093cc2c40c692937f844681a7e784805c6729418 | |
| parent | 3b4268379001f7f74989461183660a90a875f683 (diff) | |
| download | coreboot-88164787ee7e7d9e13d5a9b95093fd70394ddc46.tar.xz | |
soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTE
The value for that macro should be 1<<19. This is confirmed by the
Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE.
See Intel Atom® Processor C3000 Product Family Datasheet
(February 2018) :
https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-series/c3000-family-datasheet.html
Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>
Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33573
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/gpio_defs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h index 43e0647bd0..ae61e6d7c4 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h @@ -182,7 +182,7 @@ #define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01 // GPIO Input Route SCI -#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 10) +#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 19) #define N_PCH_GPIO_RX_SCI_ROUTE 19 #define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00 #define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01 |