diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2020-06-23 13:49:21 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-06-24 13:59:15 +0000 |
| commit | 8c28e51a16e13871941048a8312d1830379f725e (patch) | |
| tree | be494facfd6472cb95c24b670de58bfc27c51e4a | |
| parent | c1bb32f869f45766125cb459fd753726c30eee88 (diff) | |
| download | coreboot-8c28e51a16e13871941048a8312d1830379f725e.tar.xz | |
soc/amd/picasso: fix host bridge bus numbers
The host bridge's resources covering bus numbers assumed
256 buses were being decoded. However, MMCONFIG was only
covering 64 buses. This results in Linux complaining:
acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000
[bus 00-3f] only partially covers this bridge
When retrieving the host bridge's resources fix up the
bus numbers to utilize MMCONF_BUS_NUMBER Kconfig. I couldn't
keep IASL from complaining when trying to do this statically.
BUG=b:158874061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ief1901743e2c99f583ef0181490d493d23734f64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/soc/amd/picasso/acpi/sb_pci0_fch.asl | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 27c46611b3..7488b550bb 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -101,6 +101,11 @@ Method(_CRS, 0) { Subtract(Local0, TOM1, Local0) Store(Local0, MM1L) + CreateWordField(CRES, ^PSB0._MAX, BMAX) + CreateWordField(CRES, ^PSB0._LEN, BLEN) + Store(CONFIG_MMCONF_BUS_NUMBER - 1, BMAX) + Store(CONFIG_MMCONF_BUS_NUMBER, BLEN) + Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ |