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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-13 00:00:47 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-21 15:51:38 +0000 |
| commit | 8d0e88db34276d93cfbc96e1e25c571f6e49f9f8 (patch) | |
| tree | 8e395adf60dd72040f9a4a50768efd775d9e5605 | |
| parent | 1f2ae9107400390240d6338fbf0406aafd2ac01e (diff) | |
| download | coreboot-8d0e88db34276d93cfbc96e1e25c571f6e49f9f8.tar.xz | |
sb/intel/common/rcba_pirq.c: Use common RCBA acces MACROs
Change-Id: I2fe8d8388cb96e42af4f9be251a41cceeb2e4710
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27042
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/common/rcba_pirq.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/common/rcba_pirq.h | 4 |
2 files changed, 1 insertions, 4 deletions
diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 7f97971f7b..366fe08ccf 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rcba_pirq.h> +#include <southbridge/intel/common/rcba.h> #define MAX_SLOT 31 #define MIN_SLOT 19 diff --git a/src/southbridge/intel/common/rcba_pirq.h b/src/southbridge/intel/common/rcba_pirq.h index cf76fb32f5..e5ac4094f2 100644 --- a/src/southbridge/intel/common/rcba_pirq.h +++ b/src/southbridge/intel/common/rcba_pirq.h @@ -37,8 +37,4 @@ #define D20IR 0x3160 /* 16bit */ #define D19IR 0x3168 /* 16bit */ -#define DEFAULT_RCBA 0xfed1c000 - -#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x)))) - #endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */ |