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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-10-29 12:15:34 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-08 08:08:23 +0100 |
| commit | 986e85c098f6a68c2f26d1b5f81bebaff4207e28 (patch) | |
| tree | c0181e341131020e956c4e36d47e4e8cd2e1ebed | |
| parent | 31cef1f46e5caa63794709c381a68ac1a9394bbb (diff) | |
| download | coreboot-986e85c098f6a68c2f26d1b5f81bebaff4207e28.tar.xz | |
intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'
Change-Id: I1cf87b3c73d8bf8846e5870b19b089f85c299567
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7241
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/igd.c | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 373f429eb1..325edbd05b 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -246,7 +246,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) /* Enable Force Wake */ gtt_write(0x0a180, 1 << 5); gtt_write(0x0a188, 0x00010001); - gtt_poll(0x130044, 1 << 0, 1 << 0); + gtt_poll(FORCEWAKE_ACK_HSW, 1 << 0, 1 << 0); /* GT Settings */ gtt_write_regs(haswell_gt_setup); @@ -420,7 +420,7 @@ static void gma_pm_init_post_vbios(struct device *dev) /* Disable Force Wake */ gtt_write(0x0a188, 0x00010000); - gtt_poll(0x130044, 1 << 0, 0 << 0); + gtt_poll(FORCEWAKE_ACK_HSW, 1 << 0, 0 << 0); gtt_write(0x0a188, 0x00000001); } diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index eac9ac1ec1..b429758b94 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -42,7 +42,7 @@ struct reg_script haswell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 1, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), /* Enable Counters */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016), @@ -126,7 +126,7 @@ static const struct reg_script haswell_late_init_script[] = { /* Disable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001), /* Enable power well for DP and Audio */ @@ -140,7 +140,7 @@ static const struct reg_script haswell_late_init_script[] = { static const struct reg_script broadwell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 1, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), /* Enable push bus metric control and shift */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004), @@ -225,7 +225,7 @@ static const struct reg_script broadwell_late_init_script[] = { /* Disable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130044, 1, 0, GT_RETRY), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), /* Enable power well for DP and Audio */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), |