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| author | Shawn Nematbakhsh <shawnn@google.com> | 2013-06-13 19:47:47 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-02 18:06:08 +0100 |
| commit | 9a6ca071e006b46ec4472e781d177271e2e02a45 (patch) | |
| tree | 6dc38e494225a7fbe92b884bbe9f7ca5d47e40c0 | |
| parent | d9e298961f96e89a831a2993686b89b13089c76a (diff) | |
| download | coreboot-9a6ca071e006b46ec4472e781d177271e2e02a45.tar.xz | |
peppy: Add 2GB DRAM configuration.
Currently, all Peppy boards w/ '000' SPD GPIOs have 2GB DRAM. Disable
the second DRAM channel based upon the GPIOs.
Need to change / confirm this for upcoming builds.
Change-Id: I7085ddecb80626cc0bed99ba7b174c6b80350696
Reviewed-on: https://gerrit.chromium.org/gerrit/58620
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4238
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/mainboard/google/peppy/romstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index b172da2cf3..656f3bc674 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -92,6 +92,12 @@ static void copy_spd(struct pei_data *peid) if (spd_file->len < sizeof(peid->spd_data[0])) die("Missing SPD data."); + /* Index 0 is 2GB config with CH0 only. This is suject to change. + * TODO(shawnn): Check the decoding before next build. + */ + if (spd_index == 0) + peid->dimm_channel1_disabled = 3; + memcpy(peid->spd_data[0], ((char*)CBFS_SUBHEADER(spd_file)) + spd_index * sizeof(peid->spd_data[0]), |