diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-21 13:11:10 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-06-22 14:47:12 +0000 |
| commit | 9b43b89296086de1ca50f2dbaa942331c07cc95c (patch) | |
| tree | f99396ca707beb707edd3f091097cc2dcc543ed6 | |
| parent | 90cd4aaccb6e5cdc58f6335c73a29fcab16867c0 (diff) | |
| download | coreboot-9b43b89296086de1ca50f2dbaa942331c07cc95c.tar.xz | |
sb/intel/i82801{ix,jx}: Correct include guards
These southbridges are not i82801gx.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I6b4c7bc11bcb668adb0aae463defea982cf9059c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/southbridge/intel/i82801ix/i82801ix.h | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/i82801jx.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 58a49f1531..cb932e3ee5 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H -#define SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H +#ifndef SOUTHBRIDGE_INTEL_I82801IX_I82801IX_H +#define SOUTHBRIDGE_INTEL_I82801IX_I82801IX_H #define DEFAULT_TBAR ((u8 *)0xfed1b000) diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 842e049fdd..6559f8fb41 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H -#define SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H +#ifndef SOUTHBRIDGE_INTEL_I82801JX_I82801JX_H +#define SOUTHBRIDGE_INTEL_I82801JX_I82801JX_H #define DEFAULT_TBAR ((u8 *)0xfed1b000) |