mb/lenovo/thinkcentre_a58: Add mainboard

The following was tested:
- Using two DDR2 DIMMs
- S3 sleep and resume (on SeaBIOS it needs sercon disabled)
- Ethernet NIC
- Libgfxinit (native res and textmode)
- SATA
- USB
- 800MHz FSB CPU (Pentium(R) E5200 @ 2.50GHz)
- PS2 Keyboard
- Serial output

TODO:
- Add ACPI code for SuperIO devices (done in a follow-up patch)
- Add documentation

TESTED with SeaBIOS (sercon disabled), Linux 4.19

Change-Id: I483e1143e4095b8a58fed142d31ca7f233a854e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30239
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

19 files changed, 751 insertions, 0 deletions

diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig
new file mode 100644
index 0000000000..fc1c6a7934
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig
@@ -0,0 +1,50 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+if BOARD_LENOVO_THINKCENTRE_A58
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_LGA775
+	select NORTHBRIDGE_INTEL_X4X
+	select SOUTHBRIDGE_INTEL_I82801GX
+	select SUPERIO_SMSC_SMSCSUPERIO
+	select HAVE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_1024
+	select PCIEXP_ASPM
+	select PCIEXP_CLK_PM
+	select PCIEXP_L1_SUB_STATE
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
+	select HAVE_ACPI_RESUME
+	select DRIVERS_I2C_CK505
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+
+config MAINBOARD_DIR
+	string
+	default "lenovo/thinkcentre_a58"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "ThinkCentre A58"
+
+config MAX_CPUS
+	int
+	default 4
+
+endif # BOARD_LENOVO_THINKCENTRE_A58
diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig.name b/src/mainboard/lenovo/thinkcentre_a58/Kconfig.name
new file mode 100644
index 0000000000..edc44fac03
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_LENOVO_THINKCENTRE_A58
+	bool "ThinkCentre A58"
diff --git a/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc b/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc
new file mode 100644
index 0000000000..0786d6fca5
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc
@@ -0,0 +1,4 @@
+ramstage-y += cstates.c
+romstage-y += gpio.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi/ec.asl b/src/mainboard/lenovo/thinkcentre_a58/acpi/ec.asl
new file mode 100644
index 0000000000..2997587d82
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/acpi/ec.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000000..4540ce814d
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		Package() { 0x0004ffff, 0, 0, 0x14},
+		Package() { 0x0004ffff, 1, 0, 0x15},
+		Package() { 0x0004ffff, 2, 0, 0x16},
+		Package() { 0x0004ffff, 3, 0, 0x17},
+
+		Package() { 0x0008ffff, 0, 0, 0x14},
+
+		Package() { 0x000affff, 0, 0, 0x15},
+		Package() { 0x000affff, 1, 0, 0x16},
+		Package() { 0x000affff, 2, 0, 0x17},
+		Package() { 0x000affff, 3, 0, 0x14},
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
+
+		Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+
+		Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+	})
+}
diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi/platform.asl b/src/mainboard/lenovo/thinkcentre_a58/acpi/platform.asl
new file mode 100644
index 0000000000..6c92a4ed47
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/acpi/platform.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Method(_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice.  */
+	Store(Arg0, PICM)
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	/* SMI Function */
+	Store (0, TRP0)		/* Generate trap */
+	Return (SMIF)		/* Return value of SMI handler */
+}
diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl b/src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl
new file mode 100644
index 0000000000..8f414f586f
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl
@@ -0,0 +1 @@
+/* TODO */
diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c
new file mode 100644
index 0000000000..666bba63e3
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <southbridge/intel/i82801gx/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+
+	gnvs->pwrs = 1;    /* Power state (AC = 1) */
+	gnvs->cmap = 0x01; /* Enable COM 1 port */
+}
diff --git a/src/mainboard/lenovo/thinkcentre_a58/board_info.txt b/src/mainboard/lenovo/thinkcentre_a58/board_info.txt
new file mode 100644
index 0000000000..0f10a6eae1
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://support.lenovo.com/be/en/solutions/pd002373
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2009
diff --git a/src/mainboard/lenovo/thinkcentre_a58/cmos.default b/src/mainboard/lenovo/thinkcentre_a58/cmos.default
new file mode 100644
index 0000000000..8aa2238942
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/cmos.default
@@ -0,0 +1,5 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+gfx_uma_size=64M
diff --git a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout
new file mode 100644
index 0000000000..0a59868efd
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout
@@ -0,0 +1,104 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2014 Vladimir Serbinenko
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+388          4       h       0        reboot_counter
+#390          5       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+
+# coreboot config options: cpu
+#424        8       r       0        unused
+
+# coreboot config options: northbridge
+432         4        e      11        gfx_uma_size
+#435        549       r       0        unused
+
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+
+1024        144       r       0        recv_enable_results
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+11    6     64M
+11    7     128M
+11    8     256M
+11    9     96M
+11    10     160M
+11    11     224M
+11    12     352M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/lenovo/thinkcentre_a58/cstates.c b/src/mainboard/lenovo/thinkcentre_a58/cstates.c
new file mode 100644
index 0000000000..128f6558e7
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/cstates.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpigen.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+	return 0;
+}
diff --git a/src/mainboard/lenovo/thinkcentre_a58/data.vbt b/src/mainboard/lenovo/thinkcentre_a58/data.vbt
new file mode 100644
index 0000000000..705d8ede34
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/data.vbt
diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb
new file mode 100644
index 0000000000..f3f56cec1f
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb
@@ -0,0 +1,109 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/x4x		# Northbridge
+	device cpu_cluster 0 on		# APIC cluster
+		chip cpu/intel/socket_LGA775
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_1067x		# CPU
+			device lapic 0xACAC off end
+		end
+	end
+	device domain 0 on		# PCI domain
+		subsystemid 0x17aa 0x304f inherit
+		device pci 0.0 on end			# Host Bridge
+		device pci 1.0 on end			# PEG
+		device pci 2.0 on end			# Integrated graphics controller
+		chip southbridge/intel/i82801gx	# Southbridge
+			register "pirqa_routing" = "0x0b"
+			register "pirqb_routing" = "0x0b"
+			register "pirqc_routing" = "0x0b"
+			register "pirqd_routing" = "0x0b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x0b"
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi13_routing" = "1" # ??vendor
+
+			register "ide_enable_primary" = "0x1"
+			register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
+			register "gpe0_en" = "0x440"
+
+			device pci 1b.0 on end		# Audio
+			device pci 1c.0 on end		# PCIe 1
+			device pci 1c.1 on		# PCIe 2: NIC
+				device pci 00.0 on
+				end
+			end
+			device pci 1c.2 off end		# PCIe 3
+			device pci 1c.3 off end		# PCIe 4
+			device pci 1c.4 off end		# PCIe 5
+			device pci 1c.5 off end		# PCIe 6
+			device pci 1d.0 on end		# USB
+			device pci 1d.1 on end		# USB
+			device pci 1d.2 on end		# USB
+			device pci 1d.3 on end		# USB
+			device pci 1d.7 on end		# USB
+			device pci 1e.0 on end		# PCI bridge
+			device pci 1e.2 off end		# AC'97 Audio Controller
+			device pci 1e.3 off end		# AC'97 Modem Controller
+			device pci 1f.0 on		# LPC bridge
+				chip superio/smsc/smscsuperio
+					device pnp 2e.0 off end		# Floppy
+					device pnp 2e.3 on		# Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+						drq 0x74 = 3
+					end
+					device pnp 2e.4 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.5 off end		# COM2
+					device pnp 2e.7 on		# Keyboard
+						io 0x60 = 0x60 # Can't read this back
+						io 0x62 = 0x64 # Can't read this back
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.a on		# Runtime Regs
+						io 0x60 = 0x0a00
+					end
+				end # smscsuperio
+			end
+			device pci 1f.1 on end	# PATA/IDE
+			device pci 1f.2 on end	# SATA
+			device pci 1f.3 on	# SMbus
+				chip drivers/i2c/at24rf08c
+					device i2c 54 on end
+					device i2c 55 on end
+					device i2c 56 on end
+					device i2c 57 on end
+				end
+				chip drivers/i2c/ck505
+					register "mask" = "{ 0x00, 0x80 }"
+					register "regs" = "{ 0x00, 0x80 }"
+					device i2c 69 on end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl
new file mode 100644
index 0000000000..4eade3dfbb
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/dsdt.asl
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/i82801gx/i82801gx.h>
+
+#include <arch/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20090419	// OEM revision
+)
+{
+	// global NVS and variables
+	#include "acpi/platform.asl"
+	#include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/x4x/acpi/x4x.asl>
+			#include <southbridge/intel/i82801gx/acpi/ich7.asl>
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/thinkcentre_a58/gma-mainboard.ads b/src/mainboard/lenovo/thinkcentre_a58/gma-mainboard.ads
new file mode 100644
index 0000000000..bd14b285a9
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/gma-mainboard.ads
@@ -0,0 +1,27 @@
+--
+-- This file is part of the coreboot project.
+--
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/thinkcentre_a58/gpio.c b/src/mainboard/lenovo/thinkcentre_a58/gpio.c
new file mode 100644
index 0000000000..bd3d581faa
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/gpio.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_GPIO,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_GPIO,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_GPIO,
+	.gpio26 = GPIO_MODE_GPIO,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_OUTPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio9 = GPIO_DIR_OUTPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_OUTPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio18 = GPIO_DIR_OUTPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio25 = GPIO_DIR_OUTPUT,
+	.gpio26 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio7 = GPIO_LEVEL_HIGH,
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio9 = GPIO_LEVEL_LOW,
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_HIGH,
+	.gpio16 = GPIO_LEVEL_LOW,
+	.gpio18 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio25 = GPIO_LEVEL_HIGH,
+	.gpio26 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio6 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+	},
+};
diff --git a/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c
new file mode 100644
index 0000000000..94ffcfe4a8
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	/* Realtek ALC662 rev1 */
+	0x10ec0662, /* Vendor ID */
+	0x17aa304f, /* Subsystem ID */
+	10, /* Number of entries */
+
+	/* Pin Widget Verb Table */
+
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x99130120),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19830),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19831),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x0221401f),
+	AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);
+const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
new file mode 100644
index 0000000000..8d62d08ea6
--- /dev/null
+++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <southbridge/intel/common/gpio.h>
+#include <northbridge/intel/x4x/x4x.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <superio/smsc/smscsuperio/smscsuperio.h>
+#include <lib.h>
+#include <arch/stages.h>
+#include <northbridge/intel/x4x/iomap.h>
+#include <device/pnp_def.h>
+#include <timestamp.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+#define LPC_DEV PCI_DEV(0, 0x1f, 0)
+
+static void mb_lpc_setup(void)
+{
+	u32 reg32;
+	/* Set the value for GPIO base address register and enable GPIO. */
+	pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
+	pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
+
+	setup_pch_gpios(&mainboard_gpio_map);
+
+	/* Enable IOAPIC */
+	RCBA8(0x31ff) = 0x03;
+	RCBA8(0x31ff);
+
+	reg32 = RCBA32(GCS);
+	reg32 |= (1 << 5);
+	RCBA32(GCS) = reg32;
+	RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD
+		| FD_ACAUD | 1;
+	RCBA32(CG) = 0x00000001;
+}
+
+static void ich7_enable_lpc(void)
+{
+	pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0);
+	/* Fixed IO decode ranges */
+	pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010);
+	/* LPC enable devices */
+	pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
+			   | FDD_LPC_EN | LPT_LPC_EN |  COMA_LPC_EN);
+	/* IO decode range: HWM on 0xa00 */
+	pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01);
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+	//                          ch0      ch1
+	const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
+	u8 boot_path = 0;
+	u8 s3_resume;
+
+	timestamp_init(get_initial_timestamp());
+	timestamp_add_now(TS_START_ROMSTAGE);
+
+	/* Set southbridge and Super I/O GPIOs. */
+	ich7_enable_lpc();
+	mb_lpc_setup();
+	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	console_init();
+
+	report_bist_failure(bist);
+	enable_smbus();
+
+	x4x_early_init();
+
+	s3_resume = southbridge_detect_s3_resume();
+	if (s3_resume)
+		boot_path = BOOT_PATH_RESUME;
+	if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
+		boot_path = BOOT_PATH_WARM_RESET;
+
+	printk(BIOS_DEBUG, "Initializing memory\n");
+	timestamp_add_now(TS_BEFORE_INITRAM);
+	sdram_initialize(boot_path, spd_addrmap);
+	timestamp_add_now(TS_AFTER_INITRAM);
+	quick_ram_check();
+	printk(BIOS_DEBUG, "Memory initialized\n");
+
+	x4x_late_init(s3_resume);
+
+	printk(BIOS_DEBUG, "x4x late init complete\n");
+
+}