diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-07-24 13:13:46 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-14 15:13:31 +0200 |
| commit | ab16b336642a5a08ac41b5f0148e48b47ded30ec (patch) | |
| tree | 2a461b82707bd885035b38ab1a4aa157797e63a2 | |
| parent | 9506aea3511d626da936df0cee431b6dcabb8734 (diff) | |
| download | coreboot-ab16b336642a5a08ac41b5f0148e48b47ded30ec.tar.xz | |
skylake: use native gpio configuration for uart
Instead of open coding the UART2 gpio configuration use
the support library.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I9637cb995d51b67eb320650d92f8518de0280dca
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289801
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I7f0e6599df983323f773f1ec6600537c20c15b11
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11176
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | src/soc/intel/skylake/romstage/uart.c | 63 |
1 files changed, 6 insertions, 57 deletions
diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c index 4dad8f662c..d0d5ada7ec 100644 --- a/src/soc/intel/skylake/romstage/uart.c +++ b/src/soc/intel/skylake/romstage/uart.c @@ -28,7 +28,11 @@ #include <soc/serialio.h> #include <gpio.h> -static void uartgpioinit(u8 hwflowcontrol); +/* UART2 pad configuration. Support RXD and TXD for now. */ +static const struct pad_config uart2_pads[] = { +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +}; void pch_uart_init(void) { @@ -66,60 +70,5 @@ void pch_uart_init(void) pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2); - /* Configure GPIO for UART2 in native mode*/ - uartgpioinit(FALSE); -} - -/* - * GPIO modes - */ -typedef struct { - GPIO_PAD pad; - GPIO_PAD_MODE mode; -} GPIO_PAD_NATIVE_FUNCTION; - -/* - * GPP_C Community for UART2 GPIO - * pin order RXD/TXD/RTSB/CTSB - */ -static const GPIO_PAD_NATIVE_FUNCTION uartgpio[] = { - {GPIO_LP_GPP_C20, GpioPadModeNative1}, - {GPIO_LP_GPP_C21, GpioPadModeNative1}, - {GPIO_LP_GPP_C22, GpioPadModeNative1}, - {GPIO_LP_GPP_C23, GpioPadModeNative1} -}; - -/* - * GPIO config registers - */ -static const GPIO_GROUP_INFO gpio_group_info = { - PID_GPIOCOM1, - R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET, - V_PCH_GPIO_GPP_C_PAD_MAX, - R_PCH_PCR_GPIO_GPP_C_SMI_STS, - R_PCH_PCR_GPIO_GPP_C_SMI_EN -}; - -static void uartgpioinit(u8 hwflowcontrol) -{ - u32 index, pinsused, dw0reg, dw0regmask, padcfgreg, padnumber; - - if (hwflowcontrol) - pinsused = PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER; - else - pinsused = PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL; - - for (index = 0; index < pinsused; index++) { - padnumber = GPIO_GET_PAD_NUMBER(uartgpio[index].pad); - padcfgreg = 0x8 * padnumber + gpio_group_info.padcfgoffset; - dw0regmask = (uartgpio[index].mode & GPIO_CONF_PAD_MODE_MASK) - >> GPIO_CONF_PAD_MODE_BIT_POS; - dw0regmask = (GpioHardwareDefault == dw0regmask) ? - 0x0 : B_PCH_GPIO_PAD_MODE; - dw0reg = (((uartgpio[index].mode & GPIO_CONF_PAD_MODE_MASK) >> - (GPIO_CONF_PAD_MODE_BIT_POS + 1)) << N_PCH_GPIO_PAD_MODE); - - pcr_andthenor32(gpio_group_info.community, padcfgreg, - ~(u32)dw0regmask, (u32)dw0reg); - } + gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); } |