diff options
| author | Mike Loptien <mike.loptien@se-eng.com> | 2013-02-22 13:18:31 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-02-23 01:16:50 +0100 |
| commit | ac529b1e15a2872b6e2894b0661fb49b11c95169 (patch) | |
| tree | cc9daf7d7652f2af7ea71c12e12135a775de61bf | |
| parent | d6682e88afc31f0d05f74638c28f6cc60fa2ba69 (diff) | |
| download | coreboot-ac529b1e15a2872b6e2894b0661fb49b11c95169.tar.xz | |
AMD/Persimmon: Add RTC init to CIMX SB800
Adding RTC init code to the Southbridge initialization
code in 'late.c'. This initializes the RTC so that the
Date Alarm register is set to a valid value (0x00) at
startup. By setting the Date Alarm register to 0x00,
it does not get evaluated along with the seconds,
minutes, and hours when running 'fwts s3'.
Information about fwts (Firmware Test Suite) can be
found here:
https://wiki.ubuntu.com/Kernel/Reference/fwts
This was tested on a Persimmon but will apply to
other mainboards as well.
Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2488
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/late.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index ef3a34b796..0d9b5ef347 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -128,6 +128,13 @@ static void lpc_init(device_t dev) rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + /* Initialize the real time clock. + * The 0 argument tells rtc_init not to + * update CMOS unless it is invalid. + * 1 tells rtc_init to always initialize the CMOS. + */ + rtc_init(0); + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); } |