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| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2017-11-16 13:32:29 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-19 08:07:12 +0000 |
| commit | b082670234819108a15da6239e481f5c9d8b30ec (patch) | |
| tree | e83caaf80d8726e359c7b2104d1c58d77fc8b3e0 | |
| parent | a302e7f46b582a163758bc9d53f8801e7cdb2443 (diff) | |
| download | coreboot-b082670234819108a15da6239e481f5c9d8b30ec.tar.xz | |
Kconfig: Add config for creating a second bootblock
Intel PCH/Southbridges have feature that it is possible
to have the southbridge/PCH look for the bootblock at a 64K or
128K/256K/512K/1MB (in case of newer SoCs) offset instead of
the usual top of flash.
Add configs to create a second bootblock and configure its size.
Change-Id: I4bbd19c35871891b762a0673f840858d972e129e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22533
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | Makefile.inc | 8 | ||||
| -rw-r--r-- | src/soc/intel/Kconfig | 24 |
2 files changed, 30 insertions, 2 deletions
diff --git a/Makefile.inc b/Makefile.inc index bf6c4f0103..c8fefa1d40 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -956,6 +956,9 @@ $(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL) echo " FMAP $(FMAPTOOL) -h $(obj)/fmap_config.h $< $@" $(FMAPTOOL) -h $(obj)/fmap_config.h -R $(obj)/fmap.desc $< $@ +ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) +TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE) +endif ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) @@ -964,7 +967,8 @@ ifeq ($(CONFIG_ARCH_X86),y) -f $(objcbfs)/bootblock.bin \ -n bootblock \ -t bootblock \ - -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) + -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ + $(TS_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp write -u \ -r BOOTBLOCK \ @@ -979,7 +983,7 @@ else # ifeq ($(CONFIG_ARCH_X86),y) -b -4 rm -f $@.tmp.2 endif # ifeq ($(CONFIG_ARCH_X86),y) - $(CBFSTOOL) $@.tmp add-master-header + $(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) $(prebuild-files) true mv $@.tmp $@ else # ifneq ($(CONFIG_UPDATE_IMAGE),y) diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index 72ad3e0bd5..fb2643ba4d 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -13,3 +13,27 @@ source "src/soc/intel/skylake/Kconfig" # Load common config source "src/soc/intel/common/Kconfig" + +config INTEL_HAS_TOP_SWAP + bool + help + Set this config if the Intel SoC supports top swap feature + +config INTEL_ADD_TOP_SWAP_BOOTBLOCK + bool "Include a Top swap bootblock" + default n + depends on INTEL_HAS_TOP_SWAP + help + Intel PCH/Southbridges have feature that it is possible to have + the southbridge/PCH look for the bootblock at a 64K or + 128K/256K/512K/1MB (in case of newer SoCs) offset + instead of the usual top of flash. + Select this to put a 'second' bootblock. + +config INTEL_TOP_SWAP_BOOTBLOCK_SIZE + hex "Size of top swap boot block" + depends on INTEL_ADD_TOP_SWAP_BOOTBLOCK + default 0x10000 + help + Set this config to a supported topswap size. + Valid sizes: 0x10000 0x20000 0x40000 0x80000 0x100000 |