soc/intel/tigerlake/acpi: Copy acpi directory from icelake

Clone entirely from Icelake

List of changes on top off initial icelake clone
1. Removed Descriptor Name for Memory mapped SPI flash and
local APIC in northbridge.asl
2. Rearranged code in gpio.asl to move RBUF object under _CRS
and made the file use ASL2.0 syntax.
3. Make use of absolute path for scs.asl
4. Remove unused smbus.asl
5. Rearranged code in nothbridge.asl to move MCRS object under _CRS,
use absolute variable path and added TODO for further clean up.
6. Refer absolute variable path in scs.asl

Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

11 files changed, 1486 insertions, 0 deletions

diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl
new file mode 100644
index 0000000000..98863e2486
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/gpio.asl
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <soc/gpio_defs.h>
+#include <soc/irq.h>
+#include <soc/pcr_ids.h>
+
+
+Device (GPIO)
+{
+	Name (_HID, "INT3455")
+	Name (_UID, 0)
+	Name (_DDN, "GPIO Controller")
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		Name (RBUF, ResourceTemplate()
+		{
+			Memory32Fixed (ReadWrite, 0, 0, COM0)
+			Memory32Fixed (ReadWrite, 0, 0, COM1)
+			Memory32Fixed (ReadWrite, 0, 0, COM2)
+			Memory32Fixed (ReadWrite, 0, 0, COM4)
+			Memory32Fixed (ReadWrite, 0, 0, COM5)
+			Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+				{ GPIO_IRQ14 }
+		})
+
+		/* GPIO Community 0 */
+		CreateDWordField (RBUF, COM0._BAS, BAS0)
+		CreateDWordField (RBUF, COM0._LEN, LEN0)
+		Store (PCRB (PID_GPIOCOM0), BAS0)
+		Store (GPIO_BASE_SIZE, LEN0)
+
+		/* GPIO Community 1 */
+		CreateDWordField (RBUF, COM1._BAS, BAS1)
+		CreateDWordField ( RBUF, COM1._LEN, LEN1)
+		Store (PCRB (PID_GPIOCOM1), BAS1)
+		Store (GPIO_BASE_SIZE, LEN1)
+
+		/* GPIO Community 2 */
+		CreateDWordField (RBUF, COM2._BAS, BAS2)
+		CreateDWordField (RBUF, COM2._LEN, LEN2)
+		Store (PCRB (PID_GPIOCOM2), BAS2)
+		Store (GPIO_BASE_SIZE, LEN2)
+
+		/* GPIO Community 4 */
+		CreateDWordField (RBUF, COM4._BAS, BAS4)
+		CreateDWordField (RBUF, COM4._LEN, LEN4)
+		Store (PCRB (PID_GPIOCOM4), BAS4)
+		Store (GPIO_BASE_SIZE, LEN4)
+
+		/* GPIO Community 5 */
+		CreateDWordField (RBUF, COM5._BAS, BAS5)
+		CreateDWordField (RBUF, COM5._LEN, LEN5)
+		Store (PCRB (PID_GPIOCOM5), BAS5)
+		Store (GPIO_BASE_SIZE, LEN5)
+
+		Return (RBUF)
+	}
+
+	Method (_STA, 0, NotSerialized)
+	{
+		Return (0xF)
+	}
+}
+
+/*
+ * Get GPIO DW0 Address
+ * Arg0 - GPIO Number
+ */
+Method (GADD, 1, NotSerialized)
+{
+	/* GPIO Community 0 */
+	If (Arg0 >= GPP_G0 && Arg0 <= GPP_A23)
+	{
+		Local0 = PID_GPIOCOM0
+		Subtract (Arg0, GPP_A0, Local1)
+	}
+	/* GPIO Community 1 */
+	If (Arg0 >= GPP_H0 && Arg0 <= GPP_F19)
+	{
+		Local0 = PID_GPIOCOM1
+		Subtract (Arg0, GPP_D0, Local1)
+	}
+	/* GPIO Community 2 */
+	If (Arg0 >= GPD0 && Arg0 <= GPD11)
+	{
+		Local0 = PID_GPIOCOM2
+		Subtract (Arg0, GPD0, Local1)
+	}
+	/* GPIO Community 4 */
+	If (Arg0 >= GPP_C0 && Arg0 <= GPP_E23)
+	{
+		Local0 = PID_GPIOCOM4
+		Subtract (Arg0, GPP_C0, Local1)
+	}
+	/* GPIO Community 05*/
+	If (Arg0 >= GPP_R0 && Arg0 <= GPP_S7)
+	{
+		Local0 = PID_GPIOCOM5
+		Subtract (Arg0, GPP_R0, Local1)
+	}
+	Store (PCRB (Local0), Local2)
+	Add (Local2, PAD_CFG_BASE, Local2)
+	Return (Add (Local2, Multiply (Local1, 16)))
+}
+
+/*
+ * Get GPIO Value
+ * Arg0 - GPIO Number
+ */
+Method (GRXS, 1, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+	And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0)
+
+	Return (Local0)
+}
diff --git a/src/soc/intel/tigerlake/acpi/northbridge.asl b/src/soc/intel/tigerlake/acpi/northbridge.asl
new file mode 100644
index 0000000000..d6c2d346c6
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/northbridge.asl
@@ -0,0 +1,342 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define BASE_32GB	0x800000000
+#define SIZE_16GB	0x400000000
+
+Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */)  // _HID: Hardware ID
+Name (_CID, EisaId ("PNP0A03") /* PCI Bus */)  // _CID: Compatible ID
+Name (_SEG, Zero)  // _SEG: PCI Segment
+Name (_UID, Zero)  // _UID: Unique ID
+
+Device (MCHC)
+{
+	Name (_ADR, 0x00000000)
+
+	OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
+	Field (MCHP, DWordAcc, NoLock, Preserve)
+	{
+		Offset(0x40),	/* EPBAR (0:0:0:40) */
+		EPEN, 1,	/* Enable */
+		, 11,
+		EPBR, 20,	/* EPBAR [31:12] */
+
+		Offset(0x48),	/* MCHBAR (0:0:0:48) */
+		MHEN, 1,	/* Enable */
+		, 14,
+		MHBR, 17,	/* MCHBAR [31:15] */
+
+		Offset(0x60),	/* PCIEXBAR (0:0:0:60) */
+		PXEN, 1,	/* Enable */
+		PXSZ, 2,	/* PCI Express Size */
+		, 23,
+		PXBR, 6,	/* PCI Express BAR [31:26] */
+
+		Offset(0x68),	/* DMIBAR (0:0:0:68) */
+		DIEN, 1,	/* Enable */
+		, 11,
+		DIBR, 20,	/* DMIBAR [31:12] */
+
+		Offset (0xa0),	/* Top of Used Memory */
+		TOM, 64,
+
+		Offset (0xa8),	/* Top of Upper Used Memory */
+		TUUD, 64,
+
+		Offset (0xbc),	/* Top of Low Used Memory */
+		TLUD, 32,
+	}
+}
+
+Method (_CRS, 0, Serialized)
+{
+	Name (MCRS, ResourceTemplate ()
+	{
+		/* Bus Numbers */
+		WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100)
+
+		/* IO Region 0 */
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8)
+
+		/* PCI Config Space */
+		Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		/* IO Region 1 */
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300)
+
+		/* VGA memory (0xa0000-0xbffff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000)
+
+		/*  OPROM reserved (0xc0000-0xc3fff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000)
+
+		/* OPROM reserved (0xc4000-0xc7fff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000)
+
+		/* OPROM reserved (0xc8000-0xcbfff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000)
+
+		/* OPROM reserved (0xcc000-0xcffff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000)
+
+		/* OPROM reserved (0xd0000-0xd3fff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000)
+
+		/* OPROM reserved (0xd4000-0xd7fff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000)
+
+		/* OPROM reserved (0xd8000-0xdbfff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000)
+
+		/* OPROM reserved (0xdc000-0xdffff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000)
+
+		/* BIOS Extension (0xe0000-0xe3fff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000)
+
+		/* BIOS Extension (0xe4000-0xe7fff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000)
+
+		/* BIOS Extension (0xe8000-0xebfff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000)
+
+		/* BIOS Extension (0xec000-0xeffff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000)
+
+		/* System BIOS (0xf0000-0xfffff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000)
+
+		/* PCI Memory Region (TLUD - 0xdfffffff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				NonCacheable, ReadWrite,
+				0x00000000, 0x00000000, 0xdfffffff, 0x00000000,
+				0xE0000000,,, PM01)
+
+		/* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */
+		QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				NonCacheable, ReadWrite,
+				0x00000000, 0x10000, 0x1ffff, 0x00000000,
+				0x10000,,, PM02)
+
+		/* PCH reserved resource (0xfc800000-0xfe7fffff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
+				0x00000000, PCH_PRESERVED_BASE_SIZE)
+
+		/* TPM Area (0xfed40000-0xfed47fff) */
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0xfed40000, 0xfed47fff, 0x00000000,
+				0x00008000)
+	})
+
+	/* Find PCI resource area in MCRS */
+	CreateDwordField (MCRS, PM01._MIN, PMIN)
+	CreateDwordField (MCRS, PM01._MAX, PMAX)
+	CreateDwordField (MCRS, PM01._LEN, PLEN)
+
+	/*
+	 * Fix up PCI memory region
+	 * Start with Top of Lower Usable DRAM
+	 */
+	Store (\_SB.PCI0.MCHC.TLUD, PMIN)
+	Add (Subtract (PMAX, PMIN), 1, PLEN)
+
+	/* Patch PM02 range based on Memory Size */
+	CreateQwordField (MCRS, PM02._MIN, MMIN)
+	CreateQwordField (MCRS, PM02._MAX, MMAX)
+	CreateQwordField (MCRS, PM02._LEN, MLEN)
+
+	Store (\_SB.PCI0.MCHC.TUUD, Local0)
+
+	If (LLessEqual (Local0, BASE_32GB)) {
+		Store (BASE_32GB, MMIN)
+		Store (SIZE_16GB, MLEN)
+	} Else {
+		Store (0, MMIN)
+		Store (0, MLEN)
+	}
+	Subtract (Add (MMIN, MLEN), 1, MMAX)
+
+	Return (MCRS)
+}
+
+/*
+ * TODO: Clean up below functions and follow ASL2.0 code syntax
+ */
+Name (EP_B, 0) /* to store EP BAR */
+Name (MH_B, 0) /* to store MCH BAR */
+Name (PC_B, 0) /* to store PCIe BAR */
+Name (PC_L, 0) /* to store PCIe BAR Length */
+Name (DM_B, 0) /* to store DMI BAR */
+
+/* Get MCH BAR */
+Method (GMHB, 0, Serialized)
+{
+	If (LEqual (MH_B, 0)) {
+		ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B)
+	}
+	Return (MH_B)
+}
+
+/* Get EP BAR */
+Method (GEPB, 0, Serialized)
+{
+	If (LEqual (EP_B, 0)) {
+		ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B)
+	}
+	Return (EP_B)
+}
+
+/* Get PCIe BAR */
+Method (GPCB, 0, Serialized)
+{
+	If (LEqual (PC_B, 0)) {
+		ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B)
+	}
+	Return (PC_B)
+}
+
+/* Get PCIe Length */
+Method (GPCL, 0, Serialized)
+{
+	If (LEqual (PC_L, 0)) {
+		ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L)
+	}
+	Return (PC_L)
+}
+
+/* Get DMI BAR */
+Method (GDMB, 0, Serialized)
+{
+	If (LEqual (DM_B, 0)) {
+		ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B)
+	}
+	Return (DM_B)
+}
+
+/* PCI Device Resource Consumption */
+Device (PDRC)
+{
+	Name (_HID, EISAID ("PNP0C02"))
+	Name (_UID, 1)
+
+	Name (BUF0, ResourceTemplate ()
+	{
+		/* MCH BAR _BAS will be updated in _CRS below according to
+		 * B0:D0:F0:Reg.48h
+		 */
+		Memory32Fixed (ReadWrite, 0, 0x08000, MCHB)
+
+		/* DMI BAR _BAS will be updated in _CRS below according to
+		 * B0:D0:F0:Reg.68h
+		 */
+		Memory32Fixed (ReadWrite, 0, 0x01000, DMIB)
+
+		/* EP BAR _BAS will be updated in _CRS below according to
+		 * B0:D0:F0:Reg.40h
+		 */
+		Memory32Fixed (ReadWrite, 0, 0x01000, EGPB)
+
+		/* PCI Express BAR _BAS and _LEN will be updated in
+		 * _CRS below according to B0:D0:F0:Reg.60h
+		 */
+		Memory32Fixed (ReadWrite, 0, 0, PCIX)
+
+		/* VTD engine memory range.
+		 */
+		Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
+
+		/* Memory mapped SPI Flash range */
+		Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000)
+
+		/* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
+		Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000)
+
+		/* HPET address decode range */
+		Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400)
+	})
+
+	Method (_CRS, 0, Serialized)
+	{
+		CreateDwordField (BUF0, ^MCHB._BAS, MBR0)
+		Store (\_SB.PCI0.GMHB (), MBR0)
+
+		CreateDwordField (BUF0, ^DMIB._BAS, DBR0)
+		Store (\_SB.PCI0.GDMB (), DBR0)
+
+		CreateDwordField (BUF0, ^EGPB._BAS, EBR0)
+		Store (\_SB.PCI0.GEPB (), EBR0)
+
+		CreateDwordField (BUF0, ^PCIX._BAS, XBR0)
+		Store (\_SB.PCI0.GPCB (), XBR0)
+
+		CreateDwordField (BUF0, ^PCIX._LEN, XSZ0)
+		Store (\_SB.PCI0.GPCL (), XSZ0)
+
+		Return (BUF0)
+	}
+}
diff --git a/src/soc/intel/tigerlake/acpi/pch_glan.asl b/src/soc/intel/tigerlake/acpi/pch_glan.asl
new file mode 100644
index 0000000000..260dd44962
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/pch_glan.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017-2108 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Gigabit Ethernet Controller 0:1f.6 */
+
+Device (GLAN)
+{
+	Name (_ADR, 0x001f0006)
+
+	Name (_S0W, 3)
+
+	Name (_PRW, Package() {GPE0_PME_B0, 4})
+
+	Method (_DSW, 3) {}
+}
diff --git a/src/soc/intel/tigerlake/acpi/pch_hda.asl b/src/soc/intel/tigerlake/acpi/pch_hda.asl
new file mode 100644
index 0000000000..708d0b56f1
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/pch_hda.asl
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Audio Controller - Device 31, Function 3 */
+
+Device (HDAS)
+{
+	Name (_ADR, 0x001f0003)
+	Name (_DDN, "Audio Controller")
+	Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))
+
+	/* Device is D3 wake capable */
+	Name (_S0W, 3)
+
+	/* NHLT Table Address populated from GNVS values */
+	Name (NBUF, ResourceTemplate () {
+		QWordMemory (ResourceConsumer, PosDecode, MinFixed,
+			     MaxFixed, NonCacheable, ReadOnly,
+			     0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI)
+	})
+
+	/*
+	 * Device Specific Method
+	 * Arg0 - UUID
+	 * Arg1 - Revision
+	 * Arg2 - Function Index
+	 */
+	Method (_DSM, 4)
+	{
+		If (LEqual (Arg0, ^UUID)) {
+			/*
+			 * Function 0: Function Support Query
+			 * Returns a bitmask of functions supported.
+			 */
+			If (LEqual (Arg2, Zero)) {
+				/*
+				 * NHLT Query only supported for revision 1 and
+				 * if NHLT address and length are set in NVS.
+				 */
+				If (LAnd (LEqual (Arg1, One),
+					  LAnd (LNotEqual (NHLA, Zero),
+						LNotEqual (NHLL, Zero)))) {
+					Return (Buffer (One) { 0x03 })
+				} Else {
+					Return (Buffer (One) { 0x01 })
+				}
+			}
+
+			/*
+			 * Function 1: Query NHLT memory address used by
+			 * Intel Offload Engine Driver to discover any non-HDA
+			 * devices that are supported by the DSP.
+			 *
+			 * Returns a pointer to NHLT table in memory.
+			 */
+			If (LEqual (Arg2, One)) {
+				CreateQWordField (NBUF, ^NHLT._MIN, NBAS)
+				CreateQWordField (NBUF, ^NHLT._MAX, NMAS)
+				CreateQWordField (NBUF, ^NHLT._LEN, NLEN)
+
+				Store (NHLA, NBAS)
+				Store (NHLA, NMAS)
+				Store (NHLL, NLEN)
+
+				Return (NBUF)
+			}
+		}
+
+		Return (Buffer (One) { 0x00 })
+	}
+}
diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
new file mode 100644
index 0000000000..19a3c12c01
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/irq.h>
+
+Name (PICP, Package () {
+	/* PCI Bridge */
+	/* cAVS, SMBus, GbE, Nothpeak */
+	Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ },
+	Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },
+	Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ },
+	Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },
+	/* SerialIo and SCS */
+	Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
+	Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
+	Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
+	Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
+	/* PCI Express Port 9-16 */
+	Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
+	Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
+	Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
+	Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
+	/* PCI Express Port 1-8 */
+	Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
+	Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
+	Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
+	Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
+	/* eMMC */
+	Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
+	/* SerialIo */
+	Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
+	Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
+	Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
+	/* SATA controller */
+	Package(){0x0017FFFF, 0, 0, SATA_IRQ },
+	/* CSME (HECI, IDE-R, Keyboard and Text redirection */
+	Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
+	Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
+	Package(){0x0016FFFF, 2, 0, IDER_IRQ },
+	Package(){0x0016FFFF, 3, 0, KT_IRQ },
+	/* SerialIo */
+	Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
+	Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
+	Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
+	Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
+	/* D20: xHCI, OTG, SRAM, CNVi WiFi */
+	Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
+	Package(){0x0014FFFF, 1, 0, OTG_IRQ },
+	Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
+	Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
+	/* Integrated Sensor Hub */
+	Package(){0x0013FFFF, 0, 0, ISH_IRQ },
+	/* Thermal */
+	Package(){0x0012FFFF, 0, 0, THERMAL_IRQ },
+	/* Host Bridge */
+	/* Root Port D1F0 */
+	Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },
+	Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },
+	Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },
+	Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },
+	/* SA IGFX Device */
+	Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
+	/* SA Thermal Device */
+	Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
+	/* SA IPU Device */
+	Package(){0x0005FFFF, 0, 0, IPU_IRQ },
+	/* SA GNA Device */
+	Package(){0x0008FFFF, 0, 0, GNA_IRQ },
+})
+
+Name (PICN, Package () {
+	/* D31: cAVS, SMBus, GbE, Nothpeak */
+	Package () { 0x001FFFFF, 0, 0, 11 },
+	Package () { 0x001FFFFF, 1, 0, 10 },
+	Package () { 0x001FFFFF, 2, 0, 11 },
+	Package () { 0x001FFFFF, 3, 0, 11 },
+	/* D30: Can't use PIC*/
+	/* D29: PCI Express Port 9-16 */
+	Package () { 0x001DFFFF, 0, 0, 11 },
+	Package () { 0x001DFFFF, 1, 0, 10 },
+	Package () { 0x001DFFFF, 2, 0, 11 },
+	Package () { 0x001DFFFF, 3, 0, 11 },
+	/* D28: PCI Express Port 1-8 */
+	Package () { 0x001CFFFF, 0, 0, 11 },
+	Package () { 0x001CFFFF, 1, 0, 10 },
+	Package () { 0x001CFFFF, 2, 0, 11 },
+	Package () { 0x001CFFFF, 3, 0, 11 },
+	/* D26: Can't use PIC*/
+	/* D25: Can't use PIC*/
+	/* D23: SATA controller */
+	Package () { 0x0017FFFF, 0, 0, 11 },
+	/* D22: CSME (HECI, IDE-R, KT redirection */
+	Package () { 0x0016FFFF, 0, 0, 11 },
+	Package () { 0x0016FFFF, 1, 0, 10 },
+	Package () { 0x0016FFFF, 2, 0, 11 },
+	Package () { 0x0016FFFF, 3, 0, 11 },
+	/* D20: xHCI, OTG, SRAM, CNVi WiFi */
+	Package () { 0x0014FFFF, 0, 0, 11 },
+	Package () { 0x0014FFFF, 1, 0, 10 },
+	Package () { 0x0014FFFF, 2, 0, 11 },
+	Package () { 0x0014FFFF, 3, 0, 11 },
+	/* D18: Can't use PIC*/
+	/* P.E.G. Root Port D1F0 */
+	Package () { 0x0001FFFF, 0, 0, 11 },
+	Package () { 0x0001FFFF, 1, 0, 10 },
+	Package () { 0x0001FFFF, 2, 0, 11 },
+	Package () { 0x0001FFFF, 3, 0, 11 },
+	/* SA IGFX Device */
+	Package () { 0x0002FFFF, 0, 0, 11 },
+	/* SA Thermal Device */
+	Package () { 0x0004FFFF, 0, 0, 11 },
+	/* SA IPU Device */
+	Package () { 0x0005FFFF, 0, 0, 11 },
+	/* SA GNA Device */
+	Package () { 0x0008FFFF, 0, 0, 11 },
+})
+
+Method (_PRT)
+{
+	If (PICM) {
+		Return (^PICP)
+	} Else {
+		Return (^PICN)
+	}
+}
diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl
new file mode 100644
index 0000000000..0191454a5d
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/pcie.asl
@@ -0,0 +1,382 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel PCH PCIe support */
+
+Method (IRQM, 1, Serialized) {
+
+	/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
+	Name (IQAA, Package () {
+		Package () { 0x0000ffff, 0, 0, 16 },
+		Package () { 0x0000ffff, 1, 0, 17 },
+		Package () { 0x0000ffff, 2, 0, 18 },
+		Package () { 0x0000ffff, 3, 0, 19 } })
+	Name (IQAP, Package () {
+		Package () { 0x0000ffff, 0, 0, 11 },
+		Package () { 0x0000ffff, 1, 0, 10 },
+		Package () { 0x0000ffff, 2, 0, 11 },
+		Package () { 0x0000ffff, 3, 0, 11 } })
+
+	/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
+	Name (IQBA, Package () {
+		Package () { 0x0000ffff, 0, 0, 17 },
+		Package () { 0x0000ffff, 1, 0, 18 },
+		Package () { 0x0000ffff, 2, 0, 19 },
+		Package () { 0x0000ffff, 3, 0, 16 } })
+	Name (IQBP, Package () {
+		Package () { 0x0000ffff, 0, 0, 10 },
+		Package () { 0x0000ffff, 1, 0, 11 },
+		Package () { 0x0000ffff, 2, 0, 11 },
+		Package () { 0x0000ffff, 3, 0, 11 } })
+
+	/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
+	Name (IQCA, Package () {
+		Package () { 0x0000ffff, 0, 0, 18 },
+		Package () { 0x0000ffff, 1, 0, 19 },
+		Package () { 0x0000ffff, 2, 0, 16 },
+		Package () { 0x0000ffff, 3, 0, 17 } })
+	Name (IQCP, Package () {
+		Package () { 0x0000ffff, 0, 0, 11 },
+		Package () { 0x0000ffff, 1, 0, 11 },
+		Package () { 0x0000ffff, 2, 0, 11 },
+		Package () { 0x0000ffff, 3, 0, 10 } })
+
+	/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
+	Name (IQDA, Package () {
+		Package () { 0x0000ffff, 0, 0, 19 },
+		Package () { 0x0000ffff, 1, 0, 16 },
+		Package () { 0x0000ffff, 2, 0, 17 },
+		Package () { 0x0000ffff, 3, 0, 18 } })
+	Name (IQDP, Package () {
+		Package () { 0x0000ffff, 0, 0, 11 },
+		Package () { 0x0000ffff, 1, 0, 11 },
+		Package () { 0x0000ffff, 2, 0, 10 },
+		Package () { 0x0000ffff, 3, 0, 11 } })
+
+	Switch (ToInteger (Arg0))
+	{
+		Case (Package () { 1, 5, 9, 13 }) {
+			If (PICM) {
+				Return (IQAA)
+			} Else {
+				Return (IQAP)
+			}
+		}
+
+		Case (Package () { 2, 6, 10, 14 }) {
+			If (PICM) {
+				Return (IQBA)
+			} Else {
+				Return (IQBP)
+			}
+		}
+
+		Case (Package () { 3, 7, 11, 15 }) {
+			If (PICM) {
+				Return (IQCA)
+			} Else {
+				Return (IQCP)
+			}
+		}
+
+		Case (Package () { 4, 8, 12, 16 }) {
+			If (PICM) {
+				Return (IQDA)
+			} Else {
+				Return (IQDP)
+			}
+		}
+
+		Default {
+			If (PICM) {
+				Return (IQDA)
+			} Else {
+				Return (IQDP)
+			}
+		}
+	}
+}
+
+Device (RP01)
+{
+	Name (_ADR, 0x001C0000)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP02)
+{
+	Name (_ADR, 0x001C0001)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP03)
+{
+	Name (_ADR, 0x001C0002)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP04)
+{
+	Name (_ADR, 0x001C0003)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP05)
+{
+	Name (_ADR, 0x001C0004)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP06)
+{
+	Name (_ADR, 0x001C0005)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP07)
+{
+	Name (_ADR, 0x001C0006)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP08)
+{
+	Name (_ADR, 0x001C0007)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP09)
+{
+	Name (_ADR, 0x001D0000)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP10)
+{
+	Name (_ADR, 0x001D0001)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP11)
+{
+	Name (_ADR, 0x001D0002)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP12)
+{
+	Name (_ADR, 0x001D0003)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP13)
+{
+	Name (_ADR, 0x001D0004)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP14)
+{
+	Name (_ADR, 0x001D0005)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP15)
+{
+	Name (_ADR, 0x001D0006)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
+
+Device (RP16)
+{
+	Name (_ADR, 0x001D0007)
+
+	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
+	Field (RPCS, AnyAcc, NoLock, Preserve)
+	{
+		, 24,
+		RPPN, 8,	/* Root Port Number */
+	}
+
+	Method (_PRT)
+	{
+		Return (IRQM (RPPN))
+	}
+}
diff --git a/src/soc/intel/tigerlake/acpi/platform.asl b/src/soc/intel/tigerlake/acpi/platform.asl
new file mode 100644
index 0000000000..dde9b13186
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/platform.asl
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+/* Generic indicator for sleep state */
+#include <soc/intel/common/acpi/platform.asl>
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method (_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice. */
+	Store (Arg0, PICM)
+}
diff --git a/src/soc/intel/tigerlake/acpi/scs.asl b/src/soc/intel/tigerlake/acpi/scs.asl
new file mode 100644
index 0000000000..a9ff93c2ca
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/scs.asl
@@ -0,0 +1,134 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/pcr_ids.h>
+
+Scope (\_SB.PCI0) {
+
+	/*
+	 * Clear register 0x1C20/0x4820
+	 * Arg0 - PCR Port ID
+	 */
+	Method(SCSC, 1, Serialized)
+	{
+		PCRA (Arg0, 0x1C20, 0x0)
+		PCRA (Arg0, 0x4820, 0x0)
+	}
+
+	/* EMMC */
+	Device(PEMC) {
+		Name(_ADR, 0x001A0000)
+		Name (_DDN, "eMMC Controller")
+		Name (TEMP, 0)
+
+		OperationRegion(SCSR, PCI_Config, 0x00, 0x100)
+		Field(SCSR, WordAcc, NoLock, Preserve) {
+			Offset (0x84),	/* PMECTRLSTATUS */
+			PMCR, 16,
+			Offset (0xA2),	/* PG_CONFIG */
+			, 2,
+			PGEN, 1,	/* PG_ENABLE */
+		}
+
+		Method(_INI) {
+			/* Clear register 0x1C20/0x4820 */
+			SCSC (PID_EMMC)
+		}
+
+		Method(_PS0, 0, Serialized) {
+			Stall (50) // Sleep 50 us
+
+			Store(0, PGEN) // Disable PG
+
+			/* Clear register 0x1C20/0x4820 */
+			SCSC (PID_EMMC)
+
+			/* Set Power State to D0 */
+			And (PMCR, 0xFFFC, PMCR)
+			Store (PMCR, TEMP)
+		}
+
+		Method(_PS3, 0, Serialized) {
+			Store(1, PGEN) // Enable PG
+
+			/* Set Power State to D3 */
+			Or (PMCR, 0x0003, PMCR)
+			Store (PMCR, TEMP)
+		}
+
+		Device (CARD)
+		{
+			Name (_ADR, 0x00000008)
+			Method (_RMV, 0, NotSerialized)
+			{
+				Return (0)
+			}
+		}
+	}
+
+	/* SD CARD */
+	Device (SDXC)
+	{
+		Name (_ADR, 0x00140005)
+		Name (_DDN, "SD Controller")
+		Name (TEMP, 0)
+
+		OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
+		Field (SDPC, WordAcc, NoLock, Preserve)
+		{
+			Offset (0x84),	/* PMECTRLSTATUS */
+			PMCR, 16,
+			Offset (0xA2),	/* PG_CONFIG */
+			, 2,
+			PGEN, 1,	/* PG_ENABLE */
+		}
+
+		Method(_INI)
+		{
+			/* Clear register 0x1C20/0x4820 */
+			SCSC (PID_SDX)
+		}
+
+		Method (_PS0, 0, Serialized)
+		{
+			Store (0, PGEN) /* Disable PG */
+
+			/* Clear register 0x1C20/0x4820 */
+			SCSC (PID_SDX)
+
+			/* Set Power State to D0 */
+			And (PMCR, 0xFFFC, PMCR)
+			Store (PMCR, TEMP)
+		}
+
+		Method (_PS3, 0, Serialized)
+		{
+			Store (1, PGEN) /* Enable PG */
+
+			/* Set Power State to D3 */
+			Or (PMCR, 0x0003, PMCR)
+			Store (PMCR, TEMP)
+		}
+
+		Device (CARD)
+		{
+			Name (_ADR, 0x00000008)
+			Method (_RMV, 0, NotSerialized)
+			{
+				Return (1)
+			}
+		}
+	} /* Device (SDXC) */
+}
diff --git a/src/soc/intel/tigerlake/acpi/serialio.asl b/src/soc/intel/tigerlake/acpi/serialio.asl
new file mode 100644
index 0000000000..0b0e3da678
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/serialio.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Serial IO Devices */
+
+Device (I2C0)
+{
+	Name (_ADR, 0x00150000)
+	Name (_DDN, "Serial IO I2C Controller 0")
+}
+
+Device (I2C1)
+{
+	Name (_ADR, 0x00150001)
+	Name (_DDN, "Serial IO I2C Controller 1")
+}
+
+Device (I2C2)
+{
+	Name (_ADR, 0x00150002)
+	Name (_DDN, "Serial IO I2C Controller 2")
+}
+
+Device (I2C3)
+{
+	Name (_ADR, 0x00150003)
+	Name (_DDN, "Serial IO I2C Controller 3")
+}
+
+Device (I2C4)
+{
+	Name (_ADR, 0x00190000)
+	Name (_DDN, "Serial IO I2C Controller 4")
+}
+
+Device (I2C5)
+{
+	Name (_ADR, 0x00190001)
+	Name (_DDN, "Serial IO I2C Controller 5")
+}
+
+Device (SPI0)
+{
+	Name (_ADR, 0x001e0002)
+	Name (_DDN, "Serial IO SPI Controller 0")
+}
+
+Device (SPI1)
+{
+	Name (_ADR, 0x001e0003)
+	Name (_DDN, "Serial IO SPI Controller 1")
+}
+
+Device (SPI2)
+{
+	Name (_ADR, 0x00120006)
+	Name (_DDN, "Serial IO SPI Controller 2")
+}
+
+Device (UAR0)
+{
+	Name (_ADR, 0x001e0000)
+	Name (_DDN, "Serial IO UART Controller 0")
+}
+
+Device (UAR1)
+{
+	Name (_ADR, 0x001e0001)
+	Name (_DDN, "Serial IO UART Controller 1")
+}
+
+Device (UAR2)
+{
+	Name (_ADR, 0x00190002)
+	Name (_DDN, "Serial IO UART Controller 2")
+}
diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl
new file mode 100644
index 0000000000..7de8ac42d3
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/southbridge.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/itss.h>
+#include <intelblocks/pcr.h>
+#include <soc/itss.h>
+#include <soc/pcr_ids.h>
+
+/* PCI IRQ assignment */
+#include "pci_irqs.asl"
+
+/* PCR access */
+#include <soc/intel/common/acpi/pcr.asl>
+
+/* eMMC, SD Card */
+#include "scs.asl"
+
+/* GPIO controller */
+#include "gpio.asl"
+
+/* ESPI 0:1f.0 */
+#include <soc/intel/common/block/acpi/acpi/lpc.asl>
+
+/* PCH HDA */
+#include "pch_hda.asl"
+
+/* PCIE Ports */
+#include "pcie.asl"
+
+/* Serial IO */
+#include "serialio.asl"
+
+/* USB XHCI 0:14.0 */
+#include "xhci.asl"
+
+/* PCI _OSC */
+#include <soc/intel/common/acpi/pci_osc.asl>
+
+/* GBe 0:1f.6 */
+#include "pch_glan.asl"
diff --git a/src/soc/intel/tigerlake/acpi/xhci.asl b/src/soc/intel/tigerlake/acpi/xhci.asl
new file mode 100644
index 0000000000..8268bd516f
--- /dev/null
+++ b/src/soc/intel/tigerlake/acpi/xhci.asl
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/gpe.h>
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+	Name (_ADR, 0x00140000)
+
+	Name (_PRW, Package () { GPE0_PME_B0, 3 })
+
+	Name (_S3D, 3)	/* D3 supported in S3 */
+	Name (_S0W, 3)	/* D3 can wake device in S0 */
+	Name (_S3W, 3)	/* D3 can wake system from S3 */
+
+	Method (_PS0, 0, Serialized)
+	{
+
+	}
+
+	Method (_PS3, 0, Serialized)
+	{
+
+	}
+
+	/* Root Hub for Tigerlake-LP PCH */
+	Device (RHUB)
+	{
+		Name (_ADR, Zero)
+
+		/* USB2 */
+		Device (HS01) { Name (_ADR, 1) }
+		Device (HS02) { Name (_ADR, 2) }
+		Device (HS03) { Name (_ADR, 3) }
+		Device (HS04) { Name (_ADR, 4) }
+		Device (HS05) { Name (_ADR, 5) }
+		Device (HS06) { Name (_ADR, 6) }
+		Device (HS07) { Name (_ADR, 7) }
+		Device (HS08) { Name (_ADR, 8) }
+		Device (HS09) { Name (_ADR, 9) }
+		Device (HS10) { Name (_ADR, 10) }
+		Device (HS11) { Name (_ADR, 11) }
+		Device (HS12) { Name (_ADR, 12) }
+
+		/* USBr */
+		Device (USR1) { Name (_ADR, 11) }
+		Device (USR2) { Name (_ADR, 12) }
+
+		/* USB3 */
+		Device (SS01) { Name (_ADR, 13) }
+		Device (SS02) { Name (_ADR, 14) }
+		Device (SS03) { Name (_ADR, 15) }
+		Device (SS04) { Name (_ADR, 16) }
+		Device (SS05) { Name (_ADR, 17) }
+		Device (SS06) { Name (_ADR, 18) }
+	}
+}