diff options
| author | Divya Chellap <divya.chellappa@intel.com> | 2017-11-24 09:22:01 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2017-11-28 05:37:16 +0000 |
| commit | b96712dfd9e99692804b4da01a4c543da2655f4c (patch) | |
| tree | 47a9cf97abb90378d2fe8a7c4d48d3e95c42b8fa | |
| parent | ec23f048d0056f432a74a1f6bc6be993a0ba4204 (diff) | |
| download | coreboot-b96712dfd9e99692804b4da01a4c543da2655f4c.tar.xz | |
mb/google/soraka: configure WLAN_PE_RST gpio in early_gpio_table
On shutdown, Soraka enters Deep S5 and not S5 state. Setting
pad reset config of a gpio to RSMRST will not preserve
the gpio config across deepSx and the gpio should be configured again.
The WLAN_PE_RST signal should be brought up early in the bootflow
for giving the device enough time to initialized before PCIE init in FSP-S.
Hence, the gpio WLAN_PE_RST (GPP_B8) pad configuration is done in
early pad configuration in bootblock also.
BUG=b:64386481
BRANCH=none
TEST= WiFi functionality across S5, S3, DeepS3, S0ix and warm/cold reboot.
Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/gpio.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 84a829447b..d861e59368 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -371,6 +371,8 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ + PAD_CFG_GPO(GPP_B8, 0, RSMRST), #if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM) /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), |