diff options
| author | Keith Hui <buurin@gmail.com> | 2017-09-04 15:47:40 -0400 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-03 15:24:24 +0000 |
| commit | b9c1a4e8d92b51881672d440ff8e00a5ba8a0ef2 (patch) | |
| tree | 26e5cba91d15addd6467eedf9c37078f8e402f06 | |
| parent | 427feecbf0003d968ac804edaac7cb25ac67b397 (diff) | |
| download | coreboot-b9c1a4e8d92b51881672d440ff8e00a5ba8a0ef2.tar.xz | |
sb/intel/i82371eb: Consolidate bootblock.c logic
The southbridge bootblock entry point bootblock_southbridge_init()
just calls i82371eb_enable_rom() which does all the work. Move all
that code into bootblock_southbridge_init() and drop the second
function.
Plus combine the 3 lines that set 3 bits in XBCS into one.
Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
| -rw-r--r-- | src/southbridge/intel/i82371eb/bootblock.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 07f94f3275..c59343df91 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -19,7 +19,7 @@ #include <device/pci_ids.h> #include "i82371eb.h" -static void i82371eb_enable_rom(void) +static void bootblock_southbridge_init(void) { u16 reg16; pci_devfn_t dev; @@ -36,14 +36,7 @@ static void i82371eb_enable_rom(void) /* Enable access to the whole ROM, disable ROM write access. */ reg16 = pci_read_config16(dev, XBCS); - reg16 |= LOWER_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE_1MB; + reg16 |= LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB; reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ pci_write_config16(dev, XBCS, reg16); } - -static void bootblock_southbridge_init(void) -{ - i82371eb_enable_rom(); -} |