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authorNico Huber <nico.h@gmx.de>2019-11-04 16:32:01 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-06 13:57:12 +0000
commitc01d0920bb75e0b2849c26421be0a3fac6bc6198 (patch)
treeec3e2cb63634c8c597dfd2ff1873917b9038a7f9
parent214661e00c15f4005fc85ba9bca859fab41ee36c (diff)
downloadcoreboot-c01d0920bb75e0b2849c26421be0a3fac6bc6198.tar.xz
arch/riscv: Rename `stages.c` to `romstage.c`
It's only used for romstage and is incompatible to ramstages. The latter get `cbmem_top` passed as a third argument now. Also drop comments that don't apply to this file anymore. Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/arch/riscv/Makefile.inc2
-rw-r--r--src/arch/riscv/romstage.c (renamed from src/arch/riscv/stages.c)9
2 files changed, 1 insertions, 10 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 16f160e8db..003852324b 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -98,7 +98,7 @@ endif #CONFIG_ARCH_BOOTBLOCK_RISCV
ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
romstage-y += boot.c
-romstage-y += stages.c
+romstage-y += romstage.c
romstage-y += misc.c
romstage-$(ARCH_RISCV_PMP) += pmp.c
romstage-y += smp.c
diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/romstage.c
index 5b27508c47..d5f5a43ce1 100644
--- a/src/arch/riscv/stages.c
+++ b/src/arch/riscv/romstage.c
@@ -14,10 +14,6 @@
*/
/*
- * This file contains entry/exit functions for each stage during coreboot
- * execution (bootblock entry and ramstage exit will depend on external
- * loading).
- *
* Entry points must be placed at the location the previous stage jumps
* to (the lowest address in the stage image). This is done by giving
* stage_entry() its own section in .text and placing it first in the
@@ -31,11 +27,6 @@
void stage_entry(int hart_id, void *fdt)
{
- /*
- * Save the FDT pointer before entering ramstage, because mscratch
- * might be overwritten in the trap handler, and there is code in
- * ramstage that generates misaligned access faults.
- */
HLS()->hart_id = hart_id;
HLS()->fdt = fdt;
smp_pause(CONFIG_RISCV_WORKING_HARTID);