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| author | Duncan Laurie <dlaurie@chromium.org> | 2012-07-13 10:11:54 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-26 20:33:45 +0200 |
| commit | c1c9435863dd4bb22d06de486527d58b8a9e0170 (patch) | |
| tree | 3a3767d7863f217e1adc67bef68a081172b3ee07 | |
| parent | 55864eff9218259335a776a139424c4d178cf14e (diff) | |
| download | coreboot-c1c9435863dd4bb22d06de486527d58b8a9e0170.tar.xz | |
Log event for abnormal management engine status
This will log if the ME is disabled or has an error.
1) disable ME via EC console: gpioset PCH_HDA_SDO 1
2) boot the device
3) read eventlog with "mosys eventlog list"
71 | 2012-07-13 10:10:55 | Management Engine | Disabled
Change-Id: I9f6ee452d2aea76e6a5ea2cd50a50ff36245692a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1345
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/include/elog.h | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me.c | 7 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me_8.x.c | 7 |
3 files changed, 11 insertions, 6 deletions
diff --git a/src/include/elog.h b/src/include/elog.h index 7d89f45d17..5a84c75d4b 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -105,6 +105,9 @@ struct elog_event_data_wake { #define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 #define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +/* Management Engine Events */ +#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 + extern int elog_init(void); extern int elog_clear(void); extern void elog_add_event_raw(u8 event_type, void *data, u8 data_size); diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 464d0fde0e..3b7f3428bc 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -35,6 +35,7 @@ #include <device/pci_def.h> #include <string.h> #include <delay.h> +#include <elog.h> #ifdef __SMM__ # include <arch/romcc_io.h> @@ -727,9 +728,9 @@ static void intel_me_init(device_t dev) case ME_RECOVERY_BIOS_PATH: case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: - /* - * TODO(dlaurie) Force recovery mode if ME is unhappy? - */ +#if CONFIG_ELOG + elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); +#endif break; } } diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 74bf1aecdb..9461d61cdf 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -35,6 +35,7 @@ #include <device/pci_def.h> #include <string.h> #include <delay.h> +#include <elog.h> #ifdef __SMM__ # include <arch/romcc_io.h> @@ -730,9 +731,9 @@ static void intel_me_init(device_t dev) case ME_RECOVERY_BIOS_PATH: case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: - /* - * TODO(dlaurie) Force recovery mode if ME is unhappy? - */ +#if CONFIG_ELOG + elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); +#endif break; } } |