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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-30 21:48:23 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-30 21:48:23 +0000 |
| commit | c269d237f93d7867c7f4cad9a4d619b56f4a3d81 (patch) | |
| tree | 4df497fda34a1ff7e0b7d4a0567997f9259b08dd | |
| parent | 495b92b78739ddc1b5eb3cd610629cfb4d62547f (diff) | |
| download | coreboot-c269d237f93d7867c7f4cad9a4d619b56f4a3d81.tar.xz | |
fix some southbridge warnings (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/southbridge/intel/i82801ax/Kconfig | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ax/i82801ax_reset.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ax/i82801ax_watchdog.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82870/p64h2_pcibridge.c | 13 |
4 files changed, 10 insertions, 7 deletions
diff --git a/src/southbridge/intel/i82801ax/Kconfig b/src/southbridge/intel/i82801ax/Kconfig index 25e2c3aa5f..daee034f0b 100644 --- a/src/southbridge/intel/i82801ax/Kconfig +++ b/src/southbridge/intel/i82801ax/Kconfig @@ -20,4 +20,6 @@ config SOUTHBRIDGE_INTEL_I82801AX bool + select HAVE_HARD_RESET + select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801ax/i82801ax_reset.c b/src/southbridge/intel/i82801ax/i82801ax_reset.c index 239a727968..b30db9d9c0 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_reset.c +++ b/src/southbridge/intel/i82801ax/i82801ax_reset.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <reset.h> #include <arch/io.h> void hard_reset(void) diff --git a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c index fb45f521c5..6a3d4947e8 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c +++ b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> +#include <watchdog.h> /* TODO: I'm fairly sure the same functionality is provided elsewhere. */ diff --git a/src/southbridge/intel/i82870/p64h2_pcibridge.c b/src/southbridge/intel/i82870/p64h2_pcibridge.c index 3c1d418fb5..a489fe53f9 100644 --- a/src/southbridge/intel/i82870/p64h2_pcibridge.c +++ b/src/southbridge/intel/i82870/p64h2_pcibridge.c @@ -8,13 +8,12 @@ static void p64h2_pcix_init(device_t dev) { - uint32_t dword; - uint16_t word; - uint8_t byte; + u32 dword; + u8 byte; - - /* The purpose of changes to HCCR, ACNF, and MTT is to speed up the - PCI bus for cards having high speed transfers. */ + /* The purpose of changes to HCCR, ACNF, and MTT is to speed + * up the PCI bus for cards having high speed transfers. + */ dword = 0xc2040002; pci_write_config32(dev, HCCR, dword); dword = 0x0000c3bf; @@ -37,4 +36,4 @@ static const struct pci_driver pcix_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82870_1F0, }; - + |