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authorKevin Chiu <Kevin.Chiu@quantatw.com>2016-11-23 18:06:39 +0800
committerMartin Roth <martinroth@google.com>2016-11-29 17:15:43 +0100
commitca387539b540fb4cbf4f4c2be860d6d8a752b7e5 (patch)
tree817ecd95a66d443dd28a6629c2ce1ac3c17aeb0b
parent5cad9883f22234faa483fa7b6e2771a558cd3c64 (diff)
downloadcoreboot-ca387539b540fb4cbf4f4c2be860d6d8a752b7e5.tar.xz
google/pyro: disable unused devices
The following devices i2c5, i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-pyro coreboot Change-Id: I3b7b96e72b82af1885926800ee99beff07755bbc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17589 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/mainboard/google/reef/variants/pyro/devicetree.cb12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index d5745b4be7..4f17f98a76 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -202,16 +202,16 @@ chip soc/intel/apollolake
device i2c 15 on end
end
end # - I2C 4
- device pci 17.1 on end # - I2C 5
- device pci 17.2 on end # - I2C 6
- device pci 17.3 on end # - I2C 7
+ device pci 17.1 off end # - I2C 5
+ device pci 17.2 off end # - I2C 6
+ device pci 17.3 off end # - I2C 7
device pci 18.0 on end # - UART 0
device pci 18.1 on end # - UART 1
device pci 18.2 on end # - UART 2
- device pci 18.3 on end # - UART 3
+ device pci 18.3 off end # - UART 3
device pci 19.0 on end # - SPI 0
- device pci 19.1 on end # - SPI 1
- device pci 19.2 on end # - SPI 2
+ device pci 19.1 off end # - SPI 1
+ device pci 19.2 off end # - SPI 2
device pci 1a.0 on end # - PWM
device pci 1b.0 on end # - SDCARD
device pci 1c.0 on end # - eMMC