Add support for SMSC MEC1308/1310 SuperI/O EC

Change-Id: If7921a66bab35f72c8455d5f0befc32a514ab417
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/825
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

7 files changed, 465 insertions, 0 deletions

diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig
index 224376bfa8..8d66fc501f 100644
--- a/src/superio/smsc/Kconfig
+++ b/src/superio/smsc/Kconfig
@@ -40,6 +40,8 @@ config SUPERIO_SMSC_SIO1007
 	bool
 config SUPERIO_SMSC_KBC1100
 	bool
+config SUPERIO_SMSC_MEC1308
+	bool
 config SUPERIO_SMSC_SMSCSUPERIO
 	bool
 config SUPERIO_SMSC_SIO1036
diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc
index bb4bf1d725..8ebdf05d60 100644
--- a/src/superio/smsc/Makefile.inc
+++ b/src/superio/smsc/Makefile.inc
@@ -29,6 +29,7 @@ subdirs-y += lpc47n227
 subdirs-y += sio10n268
 subdirs-y += sio1007
 subdirs-y += kbc1100
+subdirs-y += mec1308
 subdirs-y += smscsuperio
 subdirs-y += sio1036
 subdirs-y += sch4037
diff --git a/src/superio/smsc/mec1308/Makefile.inc b/src/superio/smsc/mec1308/Makefile.inc
new file mode 100644
index 0000000000..b2b7baab23
--- /dev/null
+++ b/src/superio/smsc/mec1308/Makefile.inc
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+ramstage-$(CONFIG_SUPERIO_SMSC_MEC1308) += superio.c
diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl
new file mode 100644
index 0000000000..96f2ef838c
--- /dev/null
+++ b/src/superio/smsc/mec1308/acpi/superio.asl
@@ -0,0 +1,261 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO) {
+	OperationRegion (SIOA, SystemIO, 0x2E, 0x02)
+	Field (SIOA, ByteAcc, NoLock, Preserve)
+	{
+		SI2E, 8,
+		SI2F, 8,
+	}
+
+	IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x07),
+		SLDN, 8,	/* Logical Device Number */
+		Offset (0x30),
+		SACT, 8,	/* Activate */
+		Offset (0x60),
+		IO0H, 8,	/* Base Address 0 MSB */
+		IO0L, 8,	/* Base Address 0 LSB */
+		Offset (0x62),
+		IO1H, 8,	/* Base Address 1 MSB */
+		IO1L, 8,	/* Base Address 1 LSB */
+		Offset (0x70),
+		IQ00, 8,	/* Interrupt Select */
+	}
+
+	Name (LPM1, 1)		/* ACPI PM1 */
+	Name (LEC1, 2)		/* EC 1 */
+	Name (LEC2, 3)		/* EC 2 */
+	Name (LSP1, 4)		/* Serial Port */
+	Name (LKBC, 7)		/* Keyboard */
+	Name (LEC0, 8)		/* EC 0 */
+	Name (LMBX, 9)		/* Mailbox */
+
+	Method (ENTR, 0, NotSerialized)
+	{
+		Store (0x55, SI2E)
+	}
+
+	Method (EXIT, 0, NotSerialized)
+	{
+		Store (0xaa, SI2E)
+	}
+
+	/* Parse activate register for an LDN */
+	Method (ISEN, 1, NotSerialized)
+	{
+		ENTR ()
+		Store (Arg0, SLDN)
+		Store (SACT, Local0)
+		EXIT ()
+
+		/* Check if it exists */
+		If (LEqual (Local0, 0xFF))
+		{
+			Return (0x00)
+		}
+
+		/* Check if activated */
+		If (LEqual (Local0, One))
+		{
+			Return (0x0F)
+		}
+		Else
+		{
+			Return (0x0D)
+		}
+	}
+
+	/* Enable an LDN via the activate register */
+	Method (SENA, 1, NotSerialized)
+	{
+		ENTR ()
+		Store (Arg0, SLDN)
+		Store (One, SACT)
+		EXIT ()
+	}
+
+	/* Disable an LDN via the activate register */
+	Method (SDIS, 1, NotSerialized)
+	{
+		ENTR ()
+		Store (Arg0, SLDN)
+		Store (Zero, SACT)
+		EXIT ()
+	}
+
+#ifdef SIO_ENABLE_SPM1
+	Device (SPM1) {
+		Name (_HID, EISAID ("PNP0C02"))
+		Name (_UID, 1)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LPM1))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08)
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SEC1
+	Device (SEC1) {
+		Name (_HID, EISAID ("PNP0C09"))
+		Name (_UID, 2)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LEC1))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04)
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SEC2
+	Device (SEC2) {
+		Name (_HID, EISAID ("PNP0C09"))
+		Name (_UID, 3)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LEC2))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04)
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SSP1
+	Device (SSP1) {
+		Name (_HID, EISAID ("PNP0501"))
+		Name (_UID, 4)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LSP1))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08)
+			IRQNoFlags () {SIO_SSP1_IRQ}
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08)
+			IRQNoFlags () {SIO_SSP1_IRQ}
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SKBC
+	Device (SKBC)		// Keyboard
+	{
+		Name (_HID, EISAID("PNP0303"))
+		Name (_CID, EISAID("PNP030B"))
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LKBC))
+		}
+
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+			IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+			IRQNoFlags () {1}
+		})
+
+		Name (_PRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+			IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+			IRQNoFlags () {1}
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SEC0
+	Device (SEC0) {
+		Name (_HID, EISAID ("PNP0C09"))
+		Name (_UID, 8)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LEC0))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04)
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SMBX
+	Device (SMBX)		// Mailbox
+	{
+		Name (_HID, EISAID("PNP0C02"))
+		Name (_UID, 9)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LMBX))
+		}
+
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34)
+		})
+
+		Name (_PRS, ResourceTemplate()
+		{
+			IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34)
+		})
+	}
+#endif
+}
diff --git a/src/superio/smsc/mec1308/chip.h b/src/superio/smsc/mec1308/chip.h
new file mode 100644
index 0000000000..3826888dd0
--- /dev/null
+++ b/src/superio/smsc/mec1308/chip.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_SMSC_MEC1308_CHIP_H
+#define SUPERIO_SMSC_MEC1308_CHIP_H
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct chip_operations;
+extern struct chip_operations superio_smsc_mec1308_ops;
+
+struct superio_smsc_mec1308_config {
+	struct pc_keyboard keyboard;
+};
+
+#endif
diff --git a/src/superio/smsc/mec1308/mec1308.h b/src/superio/smsc/mec1308/mec1308.h
new file mode 100644
index 0000000000..2b612342f2
--- /dev/null
+++ b/src/superio/smsc/mec1308/mec1308.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define MEC1308_PM1   1
+#define MEC1308_EC1   2
+#define MEC1308_EC2   3
+#define MEC1308_UART  4
+#define MEC1308_KBC   7
+#define MEC1308_EC0   8
+#define MEC1308_MBX   9
+
diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c
new file mode 100644
index 0000000000..070871d106
--- /dev/null
+++ b/src/superio/smsc/mec1308/superio.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* RAM driver for the SMSC MEC1308 Super I/O chip */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "mec1308.h"
+#if CONFIG_HAVE_ACPI_RESUME
+#include <arch/acpi.h>
+#endif
+
+static void pnp_enter_conf_state(device_t dev)
+{
+	outb(0x55, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+	outb(0xaa, dev->path.pnp.port);
+}
+
+static void mec1308_pnp_set_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void mec1308_pnp_enable_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_enable_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void mec1308_pnp_enable(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+
+	if(dev->enabled) {
+		pnp_set_enable(dev, 1);
+	}
+	else {
+		pnp_set_enable(dev, 0);
+	}
+	pnp_exit_conf_state(dev);
+}
+
+static void mec1308_init(device_t dev)
+{
+	struct superio_smsc_mec1308_config *conf = dev->chip_info;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.pnp.device) {
+	case MEC1308_KBC:
+#if CONFIG_HAVE_ACPI_RESUME
+		if (acpi_slp_type == 3)
+			return;
+#endif
+		pc_keyboard_init(&conf->keyboard);
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = mec1308_pnp_set_resources,
+	.enable_resources = mec1308_pnp_enable_resources,
+	.enable           = mec1308_pnp_enable,
+	.init             = mec1308_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, MEC1308_PM1,  PNP_IO0, { 0x7ff, 0 } },
+	{ &ops, MEC1308_EC1,  PNP_IO0, { 0x7ff, 0 } },
+	{ &ops, MEC1308_EC2,  PNP_IO0, { 0x7ff, 0 } },
+	{ &ops, MEC1308_UART, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+	{ &ops, MEC1308_KBC,  PNP_IRQ0, { 0, 0 } /* IO Fixed at 0x60/0x64 */ },
+	{ &ops, MEC1308_EC0,  PNP_IO0, { 0x7ff, 0 } },
+	{ &ops, MEC1308_MBX,  PNP_IO0, { 0x7ff, 0 } },
+};
+
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+			   ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_smsc_mec1308_ops = {
+	CHIP_NAME("SMSC MEC1308 EC SuperIO Interface")
+	.enable_dev = enable_dev
+};
+