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authorMartin Roth <martinroth@google.com>2017-10-23 11:29:35 -0600
committerMartin Roth <martinroth@google.com>2017-11-03 15:19:05 +0000
commitd540d740b6e76ece7a3fbd5d8803f652a176b50c (patch)
tree987e3c4dd96e0ada95ec7cb8f10b90b1dabe0608
parentfa7d2a07fec4ecd1564d9b84f366a5f82d967c21 (diff)
downloadcoreboot-d540d740b6e76ece7a3fbd5d8803f652a176b50c.tar.xz
mainboard/google/kahlee: Prepare for variants
Move files that are particularly specific to the mainboard into the variant directory. Files that only have small areas of mainboard specific pieces use #if to separate between the boards. Add memory.c to split out the variant board id into a weak function. Add baseboard/gpio.h to satisfy the build - this will be updated in the next commit. BUG=b:68293392 Change-Id: I7c1beb45f571f2547f3b5b0d7ec78923d0cec761 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/mainboard/google/kahlee/BiosCallOuts.c9
-rw-r--r--src/mainboard/google/kahlee/Kconfig12
-rw-r--r--src/mainboard/google/kahlee/Makefile.inc9
-rw-r--r--src/mainboard/google/kahlee/boardid.c10
-rw-r--r--src/mainboard/google/kahlee/chromeos.c5
-rw-r--r--src/mainboard/google/kahlee/ec.h6
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h37
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h24
-rw-r--r--src/mainboard/google/kahlee/variants/kahlee/Makefile.inc22
-rw-r--r--src/mainboard/google/kahlee/variants/kahlee/devicetree.cb (renamed from src/mainboard/google/kahlee/devicetree.cb)0
-rw-r--r--src/mainboard/google/kahlee/variants/kahlee/gpio.c (renamed from src/mainboard/google/kahlee/gpio.c)3
-rw-r--r--src/mainboard/google/kahlee/variants/kahlee/include/acpi/usb_oc.asl (renamed from src/mainboard/google/kahlee/acpi/usb_oc.asl)0
-rw-r--r--src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h39
-rw-r--r--src/mainboard/google/kahlee/variants/kahlee/memory.c29
14 files changed, 179 insertions, 26 deletions
diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c
index bf590ec137..f26b54e0ed 100644
--- a/src/mainboard/google/kahlee/BiosCallOuts.c
+++ b/src/mainboard/google/kahlee/BiosCallOuts.c
@@ -19,17 +19,18 @@
#include <soc/southbridge.h>
#include <stdlib.h>
-extern const GPIO_CONTROL oem_kahlee_gpio[];
+extern const GPIO_CONTROL agesa_board_gpios[];
void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
{
- FchParams_reset->EarlyOemGpioTable = (void *)oem_kahlee_gpio;
+ FchParams_reset->EarlyOemGpioTable = (void *)agesa_board_gpios;
}
void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env)
{
- FchParams_env->PostOemGpioTable = (void *)oem_kahlee_gpio;
+ FchParams_env->PostOemGpioTable = (void *)agesa_board_gpios;
/* SDHCI/MMC configuration */
- FchParams_env->Sd.SdSlotType = 1; // EMMC
+ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE))
+ FchParams_env->Sd.SdSlotType = 1; // EMMC
}
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index 76e8eada8e..ddb1955c2b 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -35,9 +35,17 @@ config MAINBOARD_DIR
string
default google/kahlee
+config VARIANT_DIR
+ string
+ default "kahlee" if BOARD_GOOGLE_KAHLEE
+
config MAINBOARD_PART_NUMBER
string
- default "Kahlee"
+ default "Kahlee" if BOARD_GOOGLE_KAHLEE
+
+config DEVICETREE
+ string
+ default "variants/${CONFIG_VARIANT_DIR}/devicetree.cb"
config MAX_CPUS
int
@@ -66,7 +74,7 @@ config CHROMEOS
config GBB_HWID
string
depends on CHROMEOS
- default "KAHLEE TEST 6421"
+ default "KAHLEE TEST 6421" if BOARD_GOOGLE_KAHLEE
config AMD_FWM_POSITION_INDEX
int
diff --git a/src/mainboard/google/kahlee/Makefile.inc b/src/mainboard/google/kahlee/Makefile.inc
index fb381bf554..131eba38c5 100644
--- a/src/mainboard/google/kahlee/Makefile.inc
+++ b/src/mainboard/google/kahlee/Makefile.inc
@@ -17,22 +17,25 @@ bootblock-y += bootblock/bootblock.c
bootblock-y += BiosCallOuts.c
bootblock-y += bootblock/OemCustomize.c
bootblock-y += ec.c
-bootblock-y += gpio.c
romstage-y += BiosCallOuts.c
romstage-y += boardid.c
romstage-y += chromeos.c
-romstage-y += gpio.c
romstage-y += OemCustomize.c
ramstage-y += BiosCallOuts.c
ramstage-y += boardid.c
ramstage-y += chromeos.c
ramstage-y += ec.c
-ramstage-y += gpio.c
ramstage-y += OemCustomize.c
verstage-y += chromeos.c
verstage-y += ec.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/kahlee/boardid.c b/src/mainboard/google/kahlee/boardid.c
index f19b032526..5b59f329bd 100644
--- a/src/mainboard/google/kahlee/boardid.c
+++ b/src/mainboard/google/kahlee/boardid.c
@@ -16,19 +16,15 @@
#include <boardid.h>
#include <console/console.h>
#include <gpio.h>
+#include <variant/gpio.h>
+#include <baseboard/variants.h>
uint8_t board_id(void)
{
MAYBE_STATIC int id = -1;
- gpio_t gpios[] = {
- GPIO_135,
- GPIO_140,
- GPIO_144,
- };
-
if (id < 0) {
- id = gpio_base2_value(gpios, ARRAY_SIZE(gpios));
+ id = variant_board_id();
printk(BIOS_SPEW, "Board ID: %#x.\n", id);
}
diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c
index 55130741d7..e74e3b9970 100644
--- a/src/mainboard/google/kahlee/chromeos.c
+++ b/src/mainboard/google/kahlee/chromeos.c
@@ -19,10 +19,7 @@
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <gpio.h>
-
-/* SPI Write protect */
-#define CROS_WP_GPIO GPIO_142
-#define GPIO_EC_IN_RW GPIO_15
+#include <variant/gpio.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
diff --git a/src/mainboard/google/kahlee/ec.h b/src/mainboard/google/kahlee/ec.h
index 495ad692e4..3986aed63c 100644
--- a/src/mainboard/google/kahlee/ec.h
+++ b/src/mainboard/google/kahlee/ec.h
@@ -18,11 +18,7 @@
#include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
-
-/* AGPIO22 -> GPE3 */
-#define EC_SCI_GPI 3
-/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */
-#define EC_SMI_GPI 23
+#include <variant/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000000..5aca3e88b5
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#ifndef __ACPI__
+#include <soc/gpio.h>
+
+# define MEM_CONFIG0 GPIO_0
+# define MEM_CONFIG1 GPIO_0
+# define MEM_CONFIG2 GPIO_0
+# define MEM_CONFIG3 GPIO_0
+
+/* SPI Write protect */
+#define CROS_WP_GPIO GPIO_0
+#define GPIO_EC_IN_RW GPIO_0
+
+#endif /* _ACPI__ */
+
+#define EC_SCI_GPI 0
+
+#define EC_SMI_GPI 0
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..3b4da2636b
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <stddef.h>
+
+size_t variant_board_id(void);
+
+#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc
new file mode 100644
index 0000000000..94f388912c
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Google, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+romstage-y += memory.c
+
+ramstage-y += gpio.c
+ramstage-y += memory.c
diff --git a/src/mainboard/google/kahlee/devicetree.cb b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb
index 4376011797..4376011797 100644
--- a/src/mainboard/google/kahlee/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb
diff --git a/src/mainboard/google/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
index 7072b13248..e25f1a1e42 100644
--- a/src/mainboard/google/kahlee/gpio.c
+++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
@@ -19,8 +19,9 @@
#include <soc/smi.h>
#include <soc/southbridge.h>
#include <stdlib.h>
+#include <variant/gpio.h>
-const GPIO_CONTROL oem_kahlee_gpio[] = {
+const GPIO_CONTROL agesa_board_gpios[] = {
/* AGPIO2 PCIE/WLAN WAKE# SCI*/
{2, Function1, FCH_GPIO_PULL_UP_ENABLE },
diff --git a/src/mainboard/google/kahlee/acpi/usb_oc.asl b/src/mainboard/google/kahlee/variants/kahlee/include/acpi/usb_oc.asl
index 068d6fd96d..068d6fd96d 100644
--- a/src/mainboard/google/kahlee/acpi/usb_oc.asl
+++ b/src/mainboard/google/kahlee/variants/kahlee/include/acpi/usb_oc.asl
diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
new file mode 100644
index 0000000000..dfb6354a3e
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __VARIANT_GPIO_H__
+#define __VARIANT_GPIO_H__
+
+#ifndef __ACPI__
+#include <soc/gpio.h>
+
+#define MEM_CONFIG0 GPIO_135
+#define MEM_CONFIG1 GPIO_140
+#define MEM_CONFIG2 GPIO_144
+
+/* SPI Write protect */
+#define CROS_WP_GPIO GPIO_142
+#define GPIO_EC_IN_RW GPIO_15
+
+#endif /* _ACPI__ */
+
+/* AGPIO22 -> GPE3 */
+#define EC_SCI_GPI 3
+
+/* TODO: Fix this */
+/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */
+#define EC_SMI_GPI 23
+
+#endif /* __VARIANT_GPIO_H__ */
diff --git a/src/mainboard/google/kahlee/variants/kahlee/memory.c b/src/mainboard/google/kahlee/variants/kahlee/memory.c
new file mode 100644
index 0000000000..4341b824b5
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/kahlee/memory.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <gpio.h> /* src/include/gpio.h */
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+
+size_t variant_board_id(void)
+{
+ gpio_t pads[] = {
+ [2] = MEM_CONFIG2,
+ [1] = MEM_CONFIG1,
+ [0] = MEM_CONFIG0,
+ };
+
+ return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+}