diff options
| author | Qii Wang <qii.wang@mediatek.com> | 2019-02-20 14:57:28 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-26 11:15:41 +0000 |
| commit | d569845964cb9769b8b6b423511c781a376be7e5 (patch) | |
| tree | 9fb74ec87f6cc59459cefdaaff04aa787953eba6 | |
| parent | 747154074c31c88842dd8f754a5a57b9a316d943 (diff) | |
| download | coreboot-d569845964cb9769b8b6b423511c781a376be7e5.tar.xz | |
mediatek/mt8183: Modify I2C source clock
This patch change i2c source clock to TOPCKGEN.
BUG=b:80501386
BRANCH=none
TEST=Boot correctly on kukui.
Change-Id: I49e0acda22dba449d0873a95ba5fae79a9cef569
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
| -rw-r--r-- | src/soc/mediatek/mt8183/pll.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 799b6ca315..19670256a1 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -345,6 +345,9 @@ void mt_pll_init(void) /* enable infrasys DCM */ setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + /* enable [11] for change i2c module source clock to TOPCKGEN */ + setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11); + /* * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! */ |