diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2015-12-08 14:26:49 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-16 23:33:45 +0100 |
| commit | d91b1dfabbeb20080cd5b70fbb0e82c6cf839a04 (patch) | |
| tree | ac230c35c7ff9898f4cc841c82a5e48e4124c6d2 | |
| parent | 27d71da71add86dd2d8dea719896fc44cd697137 (diff) | |
| download | coreboot-d91b1dfabbeb20080cd5b70fbb0e82c6cf839a04.tar.xz | |
google/lars: add nhlt support
Provide an option for including the NHLT blobs within the
lars mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted lars board.
Audio worked with MAXIM audio card.
Change-Id: I1b7836c685ebbe1498f3dbaa2eb64d5e0d4faabb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 401f1a7b23dca19712517ed1588e1390769d1271
Original-Change-Id: I6a937872a9e10d2c5ea15d5952d23e98416df092
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316092
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12961
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/mainboard/google/lars/Kconfig | 6 | ||||
| -rw-r--r-- | src/mainboard/google/lars/mainboard.c | 38 |
2 files changed, 44 insertions, 0 deletions
diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index 2bf25475d7..e227d4d375 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -52,4 +52,10 @@ config MAX_CPUS int default 8 +config INCLUDE_NHLT_BLOBS + bool "Include blobs for audio." + select NHLT_DMIC_2CH + select NHLT_MAX98357 + select NHLT_NAU88L25 + endif diff --git a/src/mainboard/google/lars/mainboard.c b/src/mainboard/google/lars/mainboard.c index bf547479a1..6725f134d3 100644 --- a/src/mainboard/google/lars/mainboard.c +++ b/src/mainboard/google/lars/mainboard.c @@ -15,8 +15,11 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> +#include <console/console.h> #include <device/device.h> #include <stdlib.h> +#include <soc/nhlt.h> #include "ec.h" static void mainboard_init(device_t dev) @@ -24,6 +27,40 @@ static void mainboard_init(device_t dev) mainboard_ec_init(); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + /* MAXIM Smart Amps for left and right. */ + if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) + printk(BIOS_ERR, "Couldn't add max98357.\n"); + + /* NAU88l25 Headset codec. */ + if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + /* * mainboard_enable is executed as first thing after * enumerate_buses(). @@ -31,6 +68,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } struct chip_operations mainboard_ops = { |