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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-24 17:01:41 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-23 10:06:01 +0000 |
| commit | da9302a2c42038594ed0127b8887c7d984cd65e1 (patch) | |
| tree | e6dee07cdc5ccf60da66ffaa86e855c961c8fd25 | |
| parent | 78fbe3d8319bc8fdf82b76378d29c6c902fd13e5 (diff) | |
| download | coreboot-da9302a2c42038594ed0127b8887c7d984cd65e1.tar.xz | |
nb/intel/sandybridge: Drop pch.h from sandybridge.h
Include pch.h in the source files instead in sandybridge.h.
Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.
Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/mainboard/asrock/b75pro3-m/romstage.c | 1 | ||||
| -rw-r--r-- | src/mainboard/compulab/intense_pc/romstage.c | 1 | ||||
| -rw-r--r-- | src/mainboard/google/link/romstage.c | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/dcp847ske/early_southbridge.c | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/dcp847ske/romstage.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/gma.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pch.asl | 1 |
9 files changed, 8 insertions, 2 deletions
diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index 51991248af..cbd26a52ac 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -17,6 +17,7 @@ #include <device/pci_ops.h> #include <device/pnp_ops.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <superio/nuvoton/nct6776/nct6776.h> #include <superio/nuvoton/common/nuvoton.h> diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index dbd28c8aff..6d0b3af8c0 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -18,6 +18,7 @@ #include <device/pci_ops.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <superio/smsc/sio1007/chip.h> +#include <southbridge/intel/bd82x6x/pch.h> #define SIO_PORT 0x164e diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 66a503d0b1..8da13080b3 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -25,6 +25,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include "ec/google/chromeec/ec.h" #include <cbfs.h> diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 510073540f..39aeb8f6e2 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -23,6 +23,7 @@ #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> #include "superio.h" #include "thermal.h" diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index 24ec912a4c..235ad228f8 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -23,6 +23,7 @@ #else #include <northbridge/intel/sandybridge/raminit.h> #endif +#include <southbridge/intel/bd82x6x/pch.h> #if !CONFIG(USE_NATIVE_RAMINIT) void mainboard_fill_pei_data(struct pei_data *pei_data) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 0d28d67602..cb6782e9b7 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -25,6 +25,7 @@ #include <drivers/intel/gma/libgfxinit.h> #include <southbridge/intel/bd82x6x/nvs.h> #include <drivers/intel/gma/opregion.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <cbmem.h> #include "chip.h" diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c066634312..050f4c2ba0 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -29,6 +29,7 @@ #include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/smbus.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <cpu/x86/msr.h> #include "raminit_native.h" diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index e315fa463f..92cb888a41 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -52,8 +52,6 @@ #define IOMMU_BASE1 0xfed90000ULL #define IOMMU_BASE2 0xfed91000ULL -#include <southbridge/intel/bd82x6x/pch.h> - /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ #include <cpu/intel/model_206ax/model_206ax.h> diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 72e284d08f..20182192f2 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -15,6 +15,7 @@ */ /* Intel Cougar Point PCH support */ +#include <southbridge/intel/bd82x6x/pch.h> Scope(\) { |