diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-09 18:39:30 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-19 19:48:43 +0000 |
| commit | e7a1e7d3c49e980774985f3f6fae697dcb129420 (patch) | |
| tree | 2d801591554cc48950c343f94467cef6f8ebcef1 | |
| parent | ed1694157c4f14d4ce60e7c053ea044aca6777fb (diff) | |
| download | coreboot-e7a1e7d3c49e980774985f3f6fae697dcb129420.tar.xz | |
soc/intel/cannonlake: Fix HECI error on reset
Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI. Also add fail safe option to reset in case
of HECI command not successful.
TEST= Force global reset from FSP and read back HECI bar in debug print.
Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/iomap.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/reset.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/romstage.c | 4 |
4 files changed, 10 insertions, 8 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 091e6f7cbc..0deece6521 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -15,7 +15,6 @@ */ #include <device/device.h> -#include <intelblocks/cse.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> @@ -194,6 +193,4 @@ void pch_early_init(void) smbus_common_init(); enable_rtc_upper_bank(); - - heci_init(HECI1_BASE_ADDRESS); } diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index add5ee8a75..22430f055b 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -63,7 +63,7 @@ #define GPIO_BASE_SIZE 0x10000 -#define HECI1_BASE_ADDRESS 0xFEDA2000 +#define HECI1_BASE_ADDRESS 0xfeda2000 /* PTT registers */ #define PTT_TXT_BASE_ADDRESS 0xfed30800 diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index ca82bd6ac4..8192e89029 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -16,10 +16,12 @@ #include <compiler.h> #include <console/console.h> #include <intelblocks/cse.h> +#include <intelblocks/pmclib.h> #include <fsp/util.h> #include <reset.h> #include <string.h> #include <timer.h> +#include <soc/pci_devs.h> /* Reset Request */ #define MKHI_GLOBAL_RESET 0x0b @@ -82,10 +84,9 @@ void do_global_reset(void) { /* Ask CSE to do the global reset */ send_heci_reset_message(); - /* - * TODO: Presumbily we shouldn't return. But if we did, fallback to - * alternative way of triggered global reset provided by pmclib. - */ + /* global reset if CSE fail to reset */ + pmc_global_reset_enable(1); + hard_reset(); } void chipset_handle_reset(uint32_t status) diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index eb72a25ea0..94b54a66d3 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -21,8 +21,10 @@ #include <cbmem.h> #include <console/console.h> #include <fsp/util.h> +#include <intelblocks/cse.h> #include <intelblocks/pmclib.h> #include <memory_info.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> @@ -41,6 +43,8 @@ asmlinkage void car_stage_entry(void) /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; |