diff options
| author | Duncan Laurie <dlaurie@google.com> | 2018-09-26 21:11:58 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-04 09:36:59 +0000 |
| commit | ecf6531c47f77cae0e5d1349319b1f2c997e994f (patch) | |
| tree | 9da5766e8ca9fb3e9f5c3fae329dfa46de53daf7 | |
| parent | d5de063dffe5c0daa56453f669af65dde09e446a (diff) | |
| download | coreboot-ecf6531c47f77cae0e5d1349319b1f2c997e994f.tar.xz | |
ec/google/chromeec: Define a sync IRQ if needed
Some boards are adding a second pin used for synchronization between
the EC and AP. This is a direct connection between the EC and the SOC
that is intended to provide a lower latency interrupt signal for
sensors on the EC.
Currently the runtime EC interrupts assert an SCI before eventually
resulting in a Notify() on the MKBP device that the sensor driver users.
These extra layers add processing time and require additional EC
communication to determine the event source.
This interface was tested on a reworked Nocturne board with modified
EC and a modified kernel driver to ensure that the interrupt asserts
as expected and can be used by the kernel driver.
Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/ec/google/chromeec/acpi/cros_ec.asl | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index d0a5b68438..befd5a73c2 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -22,6 +22,16 @@ Device (CREC) Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 }) #endif +#ifdef EC_ENABLE_SYNC_IRQ + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive) + { + EC_SYNC_IRQ + } + }) +#endif + #ifdef EC_ENABLE_MKBP_DEVICE Device (CKSC) { |