diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2018-01-15 14:21:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-01-22 13:26:36 +0000 |
| commit | f5c416c044b8f1538aea6c677b67412cbb96d784 (patch) | |
| tree | 1ee8d1357cfe187be32dfdc013d83c87e4a9ea4e | |
| parent | 7c7181fc96264fd9cf04c22ac980a42225b3b148 (diff) | |
| download | coreboot-f5c416c044b8f1538aea6c677b67412cbb96d784.tar.xz | |
mainboard/google/zoombini/variants/meowth: configure FP MCU SPI device
Configure the FP MCU interface on GSPI1.
BRANCH=none
BUG=b:71986991
TEST=boot on reworked Meowth with a ZerbleBarn board attached to
GSPI1 and see the cros_ec kernel driver detecting it.
Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/google/zoombini/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/devicetree.cb | 10 |
2 files changed, 10 insertions, 1 deletions
diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig index f09abfc3bc..813745c4f3 100644 --- a/src/mainboard/google/zoombini/Kconfig +++ b/src/mainboard/google/zoombini/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_ZOOMBINI def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC + select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index b2c1f06952..2317c90b50 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -98,7 +98,15 @@ chip soc/intel/cannonlake device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on end # GSPI #0 - device pci 1e.3 on end # GSPI #1 + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A22_IRQ)" + device spi 0 on end + end + end # GSPI #1 device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end |