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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-15 21:05:40 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-20 15:47:21 +0000 |
| commit | fa0df7d316fc9b4be825b7ad60ada844660202c6 (patch) | |
| tree | ba59a7ca703bdd82c4e9ccf11c11896f64106c37 | |
| parent | b4f1ecb3c7c0e8cc4bfefaf070e0e70b7d7bd2b9 (diff) | |
| download | coreboot-fa0df7d316fc9b4be825b7ad60ada844660202c6.tar.xz | |
AGESA fam14: Remove early PCI subsystem ID setting
Change-Id: Id4e95c68517b01647049b5cbd50bf5a3974a9c3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
| -rw-r--r-- | src/cpu/amd/agesa/family14/fixme.c | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 2b412fac1d..c9d30396aa 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -18,10 +18,6 @@ #include <AGESA.h> #include <amdlib.h> -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 - void amd_initcpuio(void) { UINT64 MsrReg; @@ -68,8 +64,6 @@ void amd_initcpuio(void) void amd_initmmio(void) { UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -79,14 +73,6 @@ void amd_initmmio(void) MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); - /* Set Ontario Link Data */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0); - PciData = 0x01308002; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); - PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); |