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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-05-03 08:30:09 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-24 11:52:28 +0000 |
| commit | fac2893584514afb1d64e71167a8564d1da26c26 (patch) | |
| tree | a281001cf187c5896297d36caf8d07a480d6b636 | |
| parent | a23aff365186ea8859e1c1c1b0f51f7566f231e9 (diff) | |
| download | coreboot-fac2893584514afb1d64e71167a8564d1da26c26.tar.xz | |
soc/intel/broadwell/adsp: Fix 8-bit write on PCI_INTERRUPT_LINE register
The PCI_INTERRUPT_LINE register is one byte wide.
Possible side effects of clearing the three bytes after PCI_INTERRUPT_LINE are unknown.
Change-Id: I64e785309b0bf7f4d74436ea12a2444092deae22
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/broadwell/adsp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 27368c0518..897f9c4ee3 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -115,7 +115,7 @@ static void adsp_init(struct device *dev) printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n"); /* Configure for PCI mode */ - pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); + pci_write_config8(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); /* Clear ACPI Interrupt Enable Bit */ pch_iobp_update(ADSP_IOBP_PCICFGCTL, |