diff options
| author | Ronald G. Minnich <rminnich@google.com> | 2013-06-19 15:46:25 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-10 22:44:21 +0200 |
| commit | 005151047ed5ab875905a5b3ee3942d09039b945 (patch) | |
| tree | 58e1c031b589e9fc98c8f3b1d4cc61663c3fec3b | |
| parent | 6b0bab916a59c6270a1f0fd53002e568052f2b45 (diff) | |
| download | coreboot-005151047ed5ab875905a5b3ee3942d09039b945.tar.xz | |
Exynos5420: add code to make sure resume will work on DRAM.
Found during a perusal of u-boot changes. It looks important.
For more info: http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=56eab63922d2b2380518238ae03e8d69e99af4fe
Change-Id: Ida2fe2a98be008a4bdfe594cf00d01a33b511b4f
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3693
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/cpu/samsung/exynos5420/bootblock.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c index d3d737e035..5cc9ef6af2 100644 --- a/src/cpu/samsung/exynos5420/bootblock.c +++ b/src/cpu/samsung/exynos5420/bootblock.c @@ -19,10 +19,28 @@ #include "clk.h" #include "wakeup.h" +#include "cpu.h" void bootblock_cpu_init(void); void bootblock_cpu_init(void) { + u32 ret; + /* + * During Suspend-Resume & S/W-Reset, as soon as PMU releases + * pad retention, CKE goes high. This causes memory contents + * not to be retained during DRAM initialization. Therfore, + * there is a new control register(0x100431e8[28]) which lets us + * release pad retention and retain the memory content until the + * initialization is complete. + */ + if (read32(((void *)INF_REG_BASE + INF_REG1_OFFSET)) == S5P_CHECK_SLEEP) { + write32(PAD_RETENTION_DRAM_COREBLK_VAL, + (void *)PAD_RETENTION_DRAM_COREBLK_OPTION); + do { + ret = read32((void *)PAD_RETENTION_DRAM_STATUS); + } while (ret != 0x1); + } + /* kick off the multi-core timer. * We want to do this as early as we can. */ |