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authorMichał Żygowski <michal.zygowski@3mdeb.com>2020-03-31 13:36:23 +0200
committerMichał Żygowski <michal.zygowski@3mdeb.com>2020-03-31 14:41:56 +0000
commit03a3404d5b9c198c4ac74eb076df108149534b19 (patch)
treed4fc5b7e4c4e843a0307f98afea931d4201c5b5a
parentb8b8ec832360ada5a313f10938bb6cfc310a11eb (diff)
downloadcoreboot-03a3404d5b9c198c4ac74eb076df108149534b19.tar.xz
mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA
Certain PCIe endpoints cause an exception inside AmdInitMid when PCIe ClockPM is enabled in AGESA PCIe initialization structures. Disable it to allow platform to boot with such devices. coreboot driver enables the ClockPM correctly on such devices anyway. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7fb13f915861c26cf773960abb12a3a1c0211cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/39970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/mainboard/pcengines/apu2/OemCustomize.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
index e47a2c8317..8b6cd038e8 100644
--- a/src/mainboard/pcengines/apu2/OemCustomize.c
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -35,7 +35,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported,
AspmL0sL1,
PCIE_PORT3_RESET_ID,
- ClkPmSupportEnabled)
+ 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{
@@ -47,7 +47,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported,
AspmL0sL1,
PCIE_NIC_RESET_ID,
- ClkPmSupportEnabled)
+ 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{
@@ -59,7 +59,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported,
AspmL0sL1,
PCIE_NIC_RESET_ID,
- ClkPmSupportEnabled)
+ 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{
@@ -71,7 +71,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported,
AspmL0sL1,
PCIE_NIC_RESET_ID,
- ClkPmSupportEnabled)
+ 0)
},
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{
@@ -83,7 +83,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported,
AspmL0sL1,
PCIE_GFX_RESET_ID,
- ClkPmSupportEnabled)
+ 0)
}
};