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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-28 11:58:36 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-03 18:06:12 +0000 |
| commit | 055d4f25d17b02a8c876094a716411e4f44f3c1a (patch) | |
| tree | 78101d9917e44d512f32cd4eef8b40e010196101 | |
| parent | f50bd6d82da0e83b9c4339a5537327d7bf41fff1 (diff) | |
| download | coreboot-055d4f25d17b02a8c876094a716411e4f44f3c1a.tar.xz | |
mb/intel/dg43gt: Program the subsystemid
Change-Id: I9f979e63378b1e0090a57849038eaafeb20d7a40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
| -rw-r--r-- | src/mainboard/intel/dg43gt/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index 70ba6bccbb..be0b911a5a 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -25,6 +25,7 @@ chip northbridge/intel/x4x # Northbridge end end device domain 0 on # PCI domain + subsystemid 0x8086 0x0028 inherit device pci 0.0 on end # Host Bridge device pci 2.0 on end # Integrated graphics controller device pci 2.1 on end # Integrated graphics controller 2 |