diff options
| author | V Sowmya <v.sowmya@intel.com> | 2020-11-13 11:48:52 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-11-18 01:26:37 +0000 |
| commit | 0759346cd6c0dcfd300eeca216e0a2d2ed76a827 (patch) | |
| tree | a400dc9848e03abb205f9d3e1c37ffaca7653d6c | |
| parent | f2e8a7ae6bb228d43d88b4cd75ee33e0b72d36ab (diff) | |
| download | coreboot-0759346cd6c0dcfd300eeca216e0a2d2ed76a827.tar.xz | |
mb/intel/jasperlake_rvp: Modify flash layout and enable CSE RW update
This patch modifies flash layout to add ME_RW_A/B to add
the CSE RW blob and also enable the CSE RW update feature for
JSLRVP
BUG=b:169077783
TEST= Built for jslrvp. Verified that CSE RW and metadata files
are included in cbfs.
Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/chromeos.fmd | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 05f45922e2..57be7f19e9 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -7,13 +7,15 @@ FLASH@0xff000000 0x1000000 { SI_BIOS@0x600000 0xA00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x2bffc0 - RW_FWID_A@0x2cffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x12ffc0 + RW_FWID_A@0x13ffc0 0x40 + ME_RW_A(CBFS)@0x140000 0x190000 } RW_SECTION_B@0x2d0000 0x2d0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x2bffc0 - RW_FWID_B@0x2cffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x12ffc0 + RW_FWID_B@0x13ffc0 0x40 + ME_RW_B(CBFS)@0x140000 0x190000 } RW_MISC@0x5a0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { |