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authorMartin Roth <martin.roth@se-eng.com>2014-12-02 21:51:03 -0700
committerMartin Roth <gaumless@gmail.com>2014-12-06 03:23:19 +0100
commit14ca52bb964794fe4251d8848a6cefe12682cce4 (patch)
tree3f9ebd59789cd73dfb344acfea175b0449b56c00
parentcf52f9761fef3a8e46ff28d6593e0d573ff1d4ac (diff)
downloadcoreboot-14ca52bb964794fe4251d8848a6cefe12682cce4.tar.xz
fsp_baytrail: Allow selection of USB controller by get_option
It was requested to be able to update XHCI vs EHCI via get_option, so I've added it here for minnow max. This could get moved to the chipset_fsp_util.c file later, but I'm adding it here for now. More checking needs to be added to this: - Are both controllers enabled in devicetree? If not, we don't want to allow the switch. Change-Id: I4d8d2229cb9fa0cd9068701454b28ffac6d8e767 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7633 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
-rw-r--r--src/mainboard/intel/minnowmax/cmos.layout6
-rw-r--r--src/mainboard/intel/minnowmax/romstage.c11
2 files changed, 16 insertions, 1 deletions
diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout
index a66818861b..c7dc88dec4 100644
--- a/src/mainboard/intel/minnowmax/cmos.layout
+++ b/src/mainboard/intel/minnowmax/cmos.layout
@@ -85,7 +85,8 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
-#411 5 r 0 unused
+411 2 e 8 use_xhci_over_ehci
+#413 3 r 0 unused
# MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -133,6 +134,9 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 EHCI
+8 1 XHCI
+8 2 Default
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c
index af63cab4e9..a14472297a 100644
--- a/src/mainboard/intel/minnowmax/romstage.c
+++ b/src/mainboard/intel/minnowmax/romstage.c
@@ -21,6 +21,8 @@
#include <baytrail/romstage.h>
#include <drivers/intel/fsp/fsp_util.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
#include "chip.h"
/**
@@ -54,6 +56,7 @@ void late_mainboard_romstage_entry()
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
{
UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
+ u8 use_xhci = UpdData->PcdEnableXhci;
/*
* Minnow Max Board : 1GB SKU uses 2Gb density memory
@@ -65,5 +68,13 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
UpdData->PcdMemoryParameters.DIMMDensity
+= (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT);
+ /* Update XHCI UPD value if required */
+ get_option(&use_xhci, "use_xhci_over_ehci");
+ if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {
+ UpdData->PcdEnableXhci = use_xhci;
+ printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n",
+ UpdData->PcdEnableXhci?"Enabled":"Disabled");
+ }
+
return;
}