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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-03-30 18:15:30 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-04-01 18:24:20 +0200 |
| commit | 15c736be05e55d0978c361306efd833f028207a2 (patch) | |
| tree | 2623e6d81823ad98cee9df5c333609364098271d | |
| parent | 808a9c223d2115d1e5ffaf9a55023f153f750180 (diff) | |
| download | coreboot-15c736be05e55d0978c361306efd833f028207a2.tar.xz | |
soc/intel/apollolake: Fix MMIO reserved ranges calculation
mmio_resource() takes memory address in kilobytes. This patch
adds resources properly.
Change-Id: Id78dcecf05ad5b2c84e5bb5445ae3a4e4ec9d419
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14203
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/intel/apollolake/northbridge.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c index 35c36c88e2..7d29c9ed45 100644 --- a/src/soc/intel/apollolake/northbridge.c +++ b/src/soc/intel/apollolake/northbridge.c @@ -30,13 +30,15 @@ static uint32_t get_bar(device_t dev, unsigned int index) static int mc_add_fixed_mmio_resources(device_t dev, int index) { + unsigned long addr; + /* PCI extended config region */ - mmio_resource(dev, index++, ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB), - PCIEX_SIZE / KiB); + addr = ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB) / KiB; + mmio_resource(dev, index++, addr, PCIEX_SIZE / KiB); /* Memory Controller Hub */ - mmio_resource(dev, index++, ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB), - MCH_BASE_SIZE / KiB); + addr = ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB) / KiB; + mmio_resource(dev, index++, addr, MCH_BASE_SIZE / KiB); return index; } |