Remove leftover Intel i82801b support

Change-Id: If85d73745ec858155c501aa637fd27a62a41dd68
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

15 files changed, 0 insertions, 984 deletions

diff --git a/src/southbridge/intel/i82801bx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig
deleted file mode 100644
index 9d25cbf5da..0000000000
--- a/src/southbridge/intel/i82801bx/Kconfig
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-config SOUTHBRIDGE_INTEL_I82801BX
-	bool
-	select IOAPIC
-	select HAVE_HARD_RESET
-	select USE_WATCHDOG_ON_BOOT
-	select SOUTHBRIDGE_INTEL_COMMON
-	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
diff --git a/src/southbridge/intel/i82801bx/Makefile.inc b/src/southbridge/intel/i82801bx/Makefile.inc
deleted file mode 100644
index 3d6b3c7238..0000000000
--- a/src/southbridge/intel/i82801bx/Makefile.inc
+++ /dev/null
@@ -1,33 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801BX),y)
-
-ramstage-y += i82801bx.c
-ramstage-y += ac97.c
-ramstage-y += ide.c
-ramstage-y += lpc.c
-ramstage-y += nic.c
-ramstage-y += pci.c
-ramstage-y += smbus.c
-ramstage-y += usb.c
-
-ramstage-y += reset.c
-ramstage-y += watchdog.c
-
-romstage-y += early_smbus.c
-
-endif
diff --git a/src/southbridge/intel/i82801bx/ac97.c b/src/southbridge/intel/i82801bx/ac97.c
deleted file mode 100644
index 834903ed64..0000000000
--- a/src/southbridge/intel/i82801bx/ac97.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Tyan Computer
- * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "i82801bx.h"
-
-static struct device_operations ac97_ops = {
-	.read_resources		= pci_dev_read_resources,
-	.set_resources		= pci_dev_set_resources,
-	.enable_resources	= pci_dev_enable_resources,
-	.init			= 0,
-	.scan_bus		= 0,
-	.enable			= i82801bx_enable,
-};
-
-/* 82801BA/BAM (ICH2/ICH2-M) */
-static const struct pci_driver i82801ba_ac97_audio __pci_driver = {
-	.ops	= &ac97_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= PCI_DEVICE_ID_INTEL_82801BA_AC97_AUDIO,
-};
-
-static const struct pci_driver i82801ba_ac97_modem __pci_driver = {
-	.ops	= &ac97_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= PCI_DEVICE_ID_INTEL_82801BA_AC97_MODEM,
-};
diff --git a/src/southbridge/intel/i82801bx/chip.h b/src/southbridge/intel/i82801bx/chip.h
deleted file mode 100644
index 79a50c8a2e..0000000000
--- a/src/southbridge/intel/i82801bx/chip.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * The i82801bx code supports: 82801BA/82801BAM (ICH2/ICH2-M)
- */
-
-#ifndef SOUTHBRIDGE_INTEL_I82801BX_CHIP_H
-#define SOUTHBRIDGE_INTEL_I82801BX_CHIP_H
-
-#include <stdint.h>
-
-struct southbridge_intel_i82801bx_config {
-	u8 pirqa_routing;
-	u8 pirqb_routing;
-	u8 pirqc_routing;
-	u8 pirqd_routing;
-	u8 pirqe_routing;
-	u8 pirqf_routing;
-	u8 pirqg_routing;
-	u8 pirqh_routing;
-
-	u8 ide0_enable;
-	u8 ide1_enable;
-};
-
-#endif
diff --git a/src/southbridge/intel/i82801bx/early_smbus.c b/src/southbridge/intel/i82801bx/early_smbus.c
deleted file mode 100644
index 103e1a35d4..0000000000
--- a/src/southbridge/intel/i82801bx/early_smbus.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Tyan Computer
- * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/pci_ids.h>
-#include <device/pci_def.h>
-#include <southbridge/intel/common/smbus.h>
-#include "i82801bx.h"
-
-void enable_smbus(void)
-{
-	device_t dev;
-
-	/* Set the SMBus device statically (D31:F3). */
-	dev = PCI_DEV(0x0, 0x1f, 0x3);
-
-	/* Set SMBus I/O base. */
-	pci_write_config32(dev, SMB_BASE,
-			   SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
-
-	/* Set SMBus enable. */
-	pci_write_config8(dev, HOSTC, HST_EN);
-
-	/* Set SMBus I/O space enable. */
-	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
-
-	/* Disable interrupt generation. */
-	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
-
-	/* Clear any lingering errors, so transactions can run. */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-
-	printk(BIOS_DEBUG, "SMBus controller enabled\n");
-}
-
-int smbus_read_byte(u8 device, u8 address)
-{
-	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
diff --git a/src/southbridge/intel/i82801bx/i82801bx.c b/src/southbridge/intel/i82801bx/i82801bx.c
deleted file mode 100644
index 163b6f4ea4..0000000000
--- a/src/southbridge/intel/i82801bx/i82801bx.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- * (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design)
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include "i82801bx.h"
-
-void i82801bx_enable(struct device *dev)
-{
-	u16 reg16, index;
-	struct device *lpc_dev;
-
-	/* Search for the 82801BA/BAM LPC device (D31:F0) on PCI bus 0. */
-	lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-	if (!lpc_dev)
-		return;
-
-	index = PCI_FUNC(dev->path.pci.devfn);
-
-	reg16 = pci_read_config16(lpc_dev, FUNC_DIS);
-	reg16 &= ~(1 << index);         /* Enable device. */
-	if (!dev->enabled)
-		reg16 |= (1 << index);  /* Disable device, if desired. */
-	pci_write_config16(lpc_dev, FUNC_DIS, reg16);
-}
-
-struct chip_operations southbridge_intel_i82801bx_ops = {
-	CHIP_NAME("Intel ICH2 (82801Bx) Series Southbridge")
-	.enable_dev = i82801bx_enable,
-};
diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h
deleted file mode 100644
index 7a6497946b..0000000000
--- a/src/southbridge/intel/i82801bx/i82801bx.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
-#define SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H
-
-#if !defined(__PRE_RAM__)
-#include "chip.h"
-extern void i82801bx_enable(struct device *dev);
-#endif
-
-#if defined(__PRE_RAM__)
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-#endif
-
-#define SMBUS_IO_BASE		0x0f00
-#define PMBASE_ADDR		0x0400
-#define GPIO_BASE_ADDR		0x0500
-
-#define SECSTS			0x1e
-
-#define PCI_DMA_CFG		0x90
-#define SERIRQ_CNTL		0x64
-#define GEN_CNTL		0xd0
-#define GEN_STS			0xd4
-#define RTC_CONF		0xd8
-#define GEN_PMCON_3		0xa4
-
-#define PMBASE			0x40
-#define ACPI_CNTL		0x44
-#define ACPI_EN			(1 << 4)
-#define BIOS_CNTL		0x4E
-#define GPIO_BASE		0x58 /* GPIO Base Address Register */
-#define GPIO_CNTL		0x5C /* GPIO Control Register */
-#define GPIO_EN			(1 << 4)
-
-#define PIRQA_ROUT		0x60
-#define PIRQB_ROUT		0x61
-#define PIRQC_ROUT		0x62
-#define PIRQD_ROUT		0x63
-#define PIRQE_ROUT		0x68
-#define PIRQF_ROUT		0x69
-#define PIRQG_ROUT		0x6A
-#define PIRQH_ROUT		0x6B
-
-#define FUNC_DIS		0xF2
-
-#define COM_DEC			0xE0 /* LPC I/F Comm. Port Decode Ranges */
-#define LPC_EN			0xE6 /* LPC IF Enables Register */
-
-// TODO: FDC_DEC etc
-
-#define SBUS_NUM		0x19
-#define SUB_BUS_NUM		0x1A
-#define SMLT			0x1B
-#define IOBASE			0x1C
-#define IOLIM			0x1D
-#define MEMBASE			0x20
-#define MEMLIM			0x22
-#define CNF			0x50
-#define MTT			0x70
-#define PCI_MAST_STS		0x82
-
-#define TCOBASE			0x60 /* TCO Base Address Register */
-#define TCO1_CNT		0x08 /* TCO1 Control Register */
-
-/* GEN_PMCON_3 bits */
-#define RTC_BATTERY_DEAD	(1 << 2)
-#define RTC_POWER_FAILED	(1 << 1)
-#define SLEEP_AFTER_POWER_FAIL	(1 << 0)
-
-/* IDE Timing registers (IDE_TIM) */
-#define IDE_TIM_PRI		0x40	/* IDE timings, primary */
-#define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
-
-/* IDE_TIM bits */
-#define IDE_DECODE_ENABLE	(1 << 15)
-
-/* SMbus */
-#define SMB_BASE		0x20
-#define HOSTC			0x40
-
-/* HOSTC bits */
-#define I2C_EN			(1 << 2)
-#define SMB_SMI_EN		(1 << 1)
-#define HST_EN			(1 << 0)
-
-#endif				/* SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H */
diff --git a/src/southbridge/intel/i82801bx/ide.c b/src/southbridge/intel/i82801bx/ide.c
deleted file mode 100644
index 05530f188b..0000000000
--- a/src/southbridge/intel/i82801bx/ide.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Tyan Computer
- * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
- * Copyright (C) 2005 Digital Design Corporation
- * (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "i82801bx.h"
-
-typedef struct southbridge_intel_i82801bx_config config_t;
-
-static void ide_init(struct device *dev)
-{
-	u16 reg16;
-	config_t *conf = dev->chip_info;
-
-	reg16 = pci_read_config16(dev, IDE_TIM_PRI);
-	reg16 &= ~IDE_DECODE_ENABLE;
-	if (!conf || conf->ide0_enable)
-		reg16 |= IDE_DECODE_ENABLE;
-	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary",
-	       (reg16 & IDE_DECODE_ENABLE) ? "on" : "off");
-	pci_write_config16(dev, IDE_TIM_PRI, reg16);
-
-	reg16 = pci_read_config16(dev, IDE_TIM_SEC);
-	reg16 &= ~IDE_DECODE_ENABLE;
-	if (!conf || conf->ide1_enable)
-		reg16 |= IDE_DECODE_ENABLE;
-	printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary",
-	       (reg16 & IDE_DECODE_ENABLE) ? "on" : "off");
-	pci_write_config16(dev, IDE_TIM_SEC, reg16);
-}
-
-static struct device_operations ide_ops = {
-	.read_resources		= pci_dev_read_resources,
-	.set_resources		= pci_dev_set_resources,
-	.enable_resources	= pci_dev_enable_resources,
-	.init			= ide_init,
-	.scan_bus		= 0,
-	.enable			= i82801bx_enable,
-};
-
-/* 82801BA/BAM (ICH2/ICH2-M) */
-static const struct pci_driver i82801ba_ide __pci_driver = {
-	.ops	= &ide_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x244b,
-};
diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c
deleted file mode 100644
index 4fbc0044ab..0000000000
--- a/src/southbridge/intel/i82801bx/lpc.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2003 Linux Networx
- * Copyright (C) 2003 SuSE Linux AG
- * Copyright (C) 2005 Tyan Computer
- * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/isa-dma.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include "i82801bx.h"
-
-#define NMI_OFF 0
-
-typedef struct southbridge_intel_i82801bx_config config_t;
-
-/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
- * 0x00 - 0000 = Reserved
- * 0x01 - 0001 = Reserved
- * 0x02 - 0010 = Reserved
- * 0x03 - 0011 = IRQ3
- * 0x04 - 0100 = IRQ4
- * 0x05 - 0101 = IRQ5
- * 0x06 - 0110 = IRQ6
- * 0x07 - 0111 = IRQ7
- * 0x08 - 1000 = Reserved
- * 0x09 - 1001 = IRQ9
- * 0x0A - 1010 = IRQ10
- * 0x0B - 1011 = IRQ11
- * 0x0C - 1100 = IRQ12
- * 0x0D - 1101 = Reserved
- * 0x0E - 1110 = IRQ14
- * 0x0F - 1111 = IRQ15
- *
- * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN)
- * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above.
- * 1 - The PIRQ is not routed to the 8259.
- */
-
-#define PIRQA 0x03
-#define PIRQB 0x04
-#define PIRQC 0x05
-#define PIRQD 0x06
-#define PIRQE 0x07
-#define PIRQF 0x09
-#define PIRQG 0x0A
-#define PIRQH 0x0B
-
-/*
- * Use 0x0ef8 for a bitmap to cover all these IRQ's.
- * Use the defined IRQ values above or set mainboard
- * specific IRQ values in your devicetree.cb.
-*/
-
-/**
- * Enable ACPI I/O range.
- *
- * @param dev PCI device with ACPI and PM BAR's
- */
-static void i82801bx_enable_acpi(struct device *dev)
-{
-	/* Set ACPI base address (I/O space). */
-	pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
-
-	/* Enable ACPI I/O range decode and ACPI power management. */
-	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
-}
-
-/**
- * Set miscellanous static southbridge features.
- *
- * @param dev PCI device with I/O APIC control registers
- */
-static void i82801bx_enable_ioapic(struct device *dev)
-{
-	u32 reg32;
-
-	reg32 = pci_read_config32(dev, GEN_CNTL);
-	reg32 |= (1 << 13);	/* Coprocessor error enable (COPR_ERR_EN) */
-	reg32 |= (3 << 7);	/* IOAPIC enable (APIC_EN) */
-	reg32 |= (1 << 2);	/* DMA collection buffer enable (DCB_EN) */
-	reg32 |= (1 << 1);	/* Delayed transaction enable (DTE) */
-	pci_write_config32(dev, GEN_CNTL, reg32);
-	printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
-
-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
-
-	/*
-	 * Select Boot Configuration register (0x03) and
-	 * use Processor System Bus (0x01) to deliver interrupts.
-	 */
-	io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
-}
-
-static void i82801bx_enable_serial_irqs(struct device *dev)
-{
-	/* Set packet length and toggle silent mode bit. */
-	pci_write_config8(dev, SERIRQ_CNTL,
-			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
-	pci_write_config8(dev, SERIRQ_CNTL,
-			  (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
-	/* TODO: Explain/#define the real meaning of these magic numbers. */
-}
-
-static void i82801bx_pirq_init(struct device *dev, uint16_t ich_model)
-{
-	u8 reg8;
-	config_t *config = dev->chip_info;
-
-	reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA;
-	pci_write_config8(dev, PIRQA_ROUT, reg8);
-
-	reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB;
-	pci_write_config8(dev, PIRQB_ROUT, reg8);
-
-	reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC;
-	pci_write_config8(dev, PIRQC_ROUT, reg8);
-
-	reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD;
-	pci_write_config8(dev, PIRQD_ROUT, reg8);
-
-
-	reg8 = (config->pirqe_routing) ? config->pirqe_routing : PIRQE;
-	pci_write_config8(dev, PIRQE_ROUT, reg8);
-
-	reg8 = (config->pirqf_routing) ? config->pirqf_routing : PIRQF;
-	pci_write_config8(dev, PIRQF_ROUT, reg8);
-
-	reg8 = (config->pirqg_routing) ? config->pirqg_routing : PIRQG;
-	pci_write_config8(dev, PIRQG_ROUT, reg8);
-
-	reg8 = (config->pirqh_routing) ? config->pirqh_routing : PIRQH;
-	pci_write_config8(dev, PIRQH_ROUT, reg8);
-}
-
-static void i82801bx_power_options(struct device *dev)
-{
-	uint8_t byte;
-	int pwr_on = -1;
-	int nmi_option;
-
-	/* power after power fail */
-	/* FIXME this doesn't work! */
-	/* Which state do we want to goto after g3 (power restored)?
-	 * 0 == S0 Full On
-	 * 1 == S5 Soft Off
-	 */
-	pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
-	printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
-
-	/* Set up NMI on errors. */
-	byte = inb(0x61);
-	byte &= ~(1 << 3);	/* IOCHK# NMI Enable */
-	byte &= ~(1 << 2);	/* PCI SERR# Enable */
-	outb(byte, 0x61);
-	byte = inb(0x70);
-
-	nmi_option = NMI_OFF;
-	get_option(&nmi_option, "nmi");
-	if (nmi_option) {
-		byte &= ~(1 << 7);	/* Set NMI. */
-		outb(byte, 0x70);
-	}
-}
-
-static void gpio_init(struct device *dev)
-{
-	/* Set the value for GPIO base address register and enable GPIO. */
-	pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
-	pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
-}
-
-static void i82801bx_rtc_init(struct device *dev)
-{
-	uint8_t reg8;
-	uint32_t reg32;
-	int rtc_failed;
-
-	reg8 = pci_read_config8(dev, GEN_PMCON_3);
-	rtc_failed = reg8 & RTC_BATTERY_DEAD;
-	if (rtc_failed) {
-		reg8 &= ~(1 << 1);	/* Preserve the power fail state. */
-		pci_write_config8(dev, GEN_PMCON_3, reg8);
-	}
-	reg32 = pci_read_config32(dev, GEN_STS);
-	rtc_failed |= reg32 & (1 << 2);
-	cmos_init(rtc_failed);
-
-	/* Enable access to the upper 128 byte bank of CMOS RAM. */
-	pci_write_config8(dev, RTC_CONF, 0x04);
-}
-
-static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask)
-{
-	uint16_t reg16;
-	int i;
-
-	reg16 = pci_read_config16(dev, PCI_DMA_CFG);
-	reg16 &= 0x300;
-	for (i = 0; i < 8; i++) {
-		if (i == 4)
-			continue;
-		reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
-	}
-	pci_write_config16(dev, PCI_DMA_CFG, reg16);
-}
-
-static void i82801bx_lpc_decode_en(struct device *dev, uint16_t ich_model)
-{
-	/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
-	 * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
-	 * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
-	 * We also need to set the value for LPC I/F Enables Register.
-	 */
-	pci_write_config8(dev, COM_DEC, 0x10);
-	pci_write_config16(dev, LPC_EN, 0x300F);
-}
-
-static void lpc_init(struct device *dev)
-{
-	uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID);
-
-	/* Set the value for PCI command register. */
-	pci_write_config16(dev, PCI_COMMAND, 0x000f);
-
-	i82801bx_enable_acpi(dev);
-
-	/* IO APIC initialization. */
-	i82801bx_enable_ioapic(dev);
-
-	i82801bx_enable_serial_irqs(dev);
-
-	/* Setup the PIRQ. */
-	i82801bx_pirq_init(dev, ich_model);
-
-	/* Setup power options. */
-	i82801bx_power_options(dev);
-
-	/* Set the state of the GPIO lines. */
-	gpio_init(dev);
-
-	/* Initialize the real time clock. */
-	i82801bx_rtc_init(dev);
-
-	/* Route DMA. */
-	i82801bx_lpc_route_dma(dev, 0xff);
-
-	/* Initialize ISA DMA. */
-	isa_dma_init();
-
-	/* Setup decode ports and LPC I/F enables. */
-	i82801bx_lpc_decode_en(dev, ich_model);
-}
-
-static void i82801bx_lpc_read_resources(struct device *dev)
-{
-	struct resource *res;
-
-	/* Get the normal PCI resources of this device. */
-	pci_dev_read_resources(dev);
-
-	/* Add an extra subtractive resource for both memory and I/O. */
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->base = 0;
-	res->size = 0x1000;
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->base = 0xff800000;
-	res->size = 0x00800000; /* 8 MB for flash */
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, 3); /* IOAPIC */
-	res->base = IO_APIC_ADDR;
-	res->size = 0x00001000;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static struct device_operations lpc_ops = {
-	.read_resources		= i82801bx_lpc_read_resources,
-	.set_resources		= pci_dev_set_resources,
-	.enable_resources	= pci_dev_enable_resources,
-	.init			= lpc_init,
-	.scan_bus		= scan_lpc_bus,
-	.enable			= i82801bx_enable,
-};
-
-/* 82801BA/BAM (ICH2/ICH2-M) */
-static const struct pci_driver i82801ba_lpc __pci_driver = {
-	.ops	= &lpc_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x2440,
-};
diff --git a/src/southbridge/intel/i82801bx/nic.c b/src/southbridge/intel/i82801bx/nic.c
deleted file mode 100644
index a1dc34c45f..0000000000
--- a/src/southbridge/intel/i82801bx/nic.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-
-static struct device_operations nic_ops = {
-	.read_resources		= pci_dev_read_resources,
-	.set_resources		= pci_dev_set_resources,
-	.enable_resources	= pci_dev_enable_resources,
-	.init			= 0,
-	.scan_bus		= 0,
-};
-
-/* 82801BA/BAM (ICH2/ICH2-M) */
-static const struct pci_driver i82801ba_nic __pci_driver = {
-	.ops	= &nic_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= PCI_DEVICE_ID_INTEL_82801BA_LAN,
-};
diff --git a/src/southbridge/intel/i82801bx/pci.c b/src/southbridge/intel/i82801bx/pci.c
deleted file mode 100644
index 2266ec3b16..0000000000
--- a/src/southbridge/intel/i82801bx/pci.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Tyan Computer
- * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "i82801bx.h"
-
-static void pci_init(struct device *dev)
-{
-	u16 reg16;
-
-	/* Clear system errors */
-	reg16 = pci_read_config16(dev, PCI_STATUS);
-	reg16 |= 0xf900;	/* Clear possible errors */
-	pci_write_config16(dev, PCI_STATUS, reg16);
-
-	reg16 = pci_read_config16(dev, SECSTS);
-	reg16 |= 0xf800;	/* Clear possible errors */
-	pci_write_config16(dev, SECSTS, reg16);
-}
-
-static struct device_operations pci_ops = {
-	.read_resources		= pci_bus_read_resources,
-	.set_resources		= pci_dev_set_resources,
-	.enable_resources	= pci_bus_enable_resources,
-	.init			= pci_init,
-	.scan_bus		= pci_scan_bridge,
-};
-
-/* 82801BA/BAM (ICH2/ICH2-M) */
-static const struct pci_driver i82801misc_pci __pci_driver = {
-	.ops	= &pci_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= 0x244e,
-};
diff --git a/src/southbridge/intel/i82801bx/reset.c b/src/southbridge/intel/i82801bx/reset.c
deleted file mode 100644
index 41b99c704d..0000000000
--- a/src/southbridge/intel/i82801bx/reset.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_hard_reset(void)
-{
-	/* Try rebooting through port 0xcf9. */
-	outb((1 << 2) | (1 << 1), 0xcf9);
-}
diff --git a/src/southbridge/intel/i82801bx/smbus.c b/src/southbridge/intel/i82801bx/smbus.c
deleted file mode 100644
index 90975cd53d..0000000000
--- a/src/southbridge/intel/i82801bx/smbus.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/smbus.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <southbridge/intel/common/smbus.h>
-#include "i82801bx.h"
-
-static int lsmbus_read_byte(struct device *dev, u8 address)
-{
-	u16 device;
-	struct resource *res;
-	struct bus *pbus;
-
-	device = dev->path.i2c.device;
-	pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
-
-	return do_smbus_read_byte(res->base, device, address);
-}
-
-static struct smbus_bus_operations lops_smbus_bus = {
-	.read_byte	= lsmbus_read_byte,
-};
-
-static const struct device_operations smbus_ops = {
-	.read_resources		= pci_dev_read_resources,
-	.set_resources		= pci_dev_set_resources,
-	.enable_resources	= pci_dev_enable_resources,
-	.init			= 0,
-	.scan_bus		= scan_smbus,
-	.enable			= i82801bx_enable,
-	.ops_smbus_bus		= &lops_smbus_bus,
-};
-
-/* 82801BA/BAM (ICH2/ICH2-M) */
-static const struct pci_driver i82801ba_smb __pci_driver = {
-	.ops	= &smbus_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= PCI_DEVICE_ID_INTEL_82801BA_SMB,
-};
diff --git a/src/southbridge/intel/i82801bx/usb.c b/src/southbridge/intel/i82801bx/usb.c
deleted file mode 100644
index 5533fb7929..0000000000
--- a/src/southbridge/intel/i82801bx/usb.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "i82801bx.h"
-
-static void usb_init(struct device *dev)
-{
-	/* TODO: Any init needed? Some ports have it, others don't. */
-}
-
-static struct device_operations usb_ops = {
-	.read_resources		= pci_dev_read_resources,
-	.set_resources		= pci_dev_set_resources,
-	.enable_resources	= pci_dev_enable_resources,
-	.init			= usb_init,
-	.scan_bus		= 0,
-	.enable			= i82801bx_enable,
-};
-
-/* 82801BA/BAM (ICH2/ICH2-M) */
-static const struct pci_driver i82801ba_usb1 __pci_driver = {
-	.ops	= &usb_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= PCI_DEVICE_ID_INTEL_82801BA_USB1,
-};
-
-static const struct pci_driver i82801ba_usb2 __pci_driver = {
-	.ops	= &usb_ops,
-	.vendor	= PCI_VENDOR_ID_INTEL,
-	.device	= PCI_DEVICE_ID_INTEL_82801BA_USB2,
-};
diff --git a/src/southbridge/intel/i82801bx/watchdog.c b/src/southbridge/intel/i82801bx/watchdog.c
deleted file mode 100644
index d0af76c030..0000000000
--- a/src/southbridge/intel/i82801bx/watchdog.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 John Dufresne <jon.dufresne@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <watchdog.h>
-
-/* TODO: I'm fairly sure the same functionality is provided elsewhere. */
-
-void watchdog_off(void)
-{
-	struct device *dev;
-	unsigned long value, base;
-
-	/* Turn off the ICH5 watchdog. */
-	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
-
-	/* Enable I/O space. */
-	value = pci_read_config16(dev, 0x04);
-	value |= (1 << 10);
-	pci_write_config16(dev, 0x04, value);
-
-	/* Get TCO base. */
-	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
-
-	/* Disable the watchdog timer. */
-	value = inw(base + 0x08);
-	value |= 1 << 11;
-	outw(value, base + 0x08);
-
-	/* Clear TCO timeout status. */
-	outw(0x0008, base + 0x04);
-	outw(0x0002, base + 0x06);
-
-	printk(BIOS_DEBUG, "ICH Watchdog disabled\n");
-}