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authorPatrick Georgi <patrick.georgi@secunet.com>2012-07-27 09:51:32 +0200
committerAnton Kochkov <anton.kochkov@gmail.com>2012-07-27 11:09:19 +0200
commit19e99f5cf1659bc3731774087de3208b4a52fd2a (patch)
treec5d25a81aed5092cde198637155e342dadeaae27
parent48fcb53c5d507ab421a5a5461722b610b6e40233 (diff)
downloadcoreboot-19e99f5cf1659bc3731774087de3208b4a52fd2a.tar.xz
libpayload: Fix typo
Change-Id: I8708703e497053aa1251f06402bd8ea59bd9d24e Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1370 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
-rw-r--r--payloads/libpayload/drivers/usb/ohci.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c
index 606e46791e..2cfabb4d4d 100644
--- a/payloads/libpayload/drivers/usb/ohci.c
+++ b/payloads/libpayload/drivers/usb/ohci.c
@@ -54,7 +54,7 @@ ohci_reset (hci_t *controller)
OHCI_INST(controller)->opreg->HcCommandStatus = HostControllerReset;
mdelay(2); /* wait 2ms */
- OCHI_INST(controller)->opreg->HcControl = 0;
+ OHCI_INST(controller)->opreg->HcControl = 0;
mdelay(10); /* wait 10ms */
}
@@ -118,7 +118,7 @@ ohci_init (pcidev_t addr)
OHCI_INST (controller)->roothub = controller->devices[0];
controller->bus_address = addr;
- /* regarding OHCI spec, Appendix A, BAR_OCHI register description, Table A-4
+ /* regarding OHCI spec, Appendix A, BAR_OHCI register description, Table A-4
* BASE ADDRESS only [31-12] bits. All other usually 0, but not all */
controller->reg_base = pci_read_config32 (controller->bus_address, 0x10) & 0xfffff000; // OHCI mandates MMIO, so bit 0 is clear
OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(controller->reg_base);