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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-05-20 17:03:23 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-10 22:22:51 +0200 |
| commit | 1a1a826276117514d7a9faf06d6ee8e1c0d099d9 (patch) | |
| tree | ee69cbcc4f8f4b3c31bf0b6eaaa41a7eedf61e0b | |
| parent | 82efc7600a6cfd5bad7600a1341d3ba4182e6324 (diff) | |
| download | coreboot-1a1a826276117514d7a9faf06d6ee8e1c0d099d9.tar.xz | |
mips: implement arch_segment_loaded callback
This change adds cache management after loading stages.
Before jumping to a new stage we should flush the data
caches to memory and invalidate instruction cache.
After all segments are loaded CBFS cache is also
flushed.
With this change all stages of coreboot are now executed
successfully. This was tested on Pistachio bring up board,
also known as Urara.
Change-Id: I86e07432c21a803ef1cfc41b633c5df42b99de90
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/10456
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/arch/mips/cache.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c index 7d96426c9a..c7a125f8d4 100644 --- a/src/arch/mips/cache.c +++ b/src/arch/mips/cache.c @@ -20,6 +20,7 @@ #include <arch/cache.h> #include <arch/cpu.h> #include <console/console.h> +#include <program_loading.h> #include <symbols.h> /* cache_op: issues cache operation for specified address */ @@ -109,3 +110,10 @@ void cache_invalidate_all(uintptr_t start, size_t size) perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD)); perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD)); } + +void arch_segment_loaded(uintptr_t start, size_t size, int flags) +{ + cache_invalidate_all(start, size); + if (flags & SEG_FINAL) + cache_invalidate_all((uintptr_t)_cbfs_cache, _cbfs_cache_size); +} |