diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2018-03-14 09:11:20 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-03-16 04:18:51 +0000 |
| commit | 211bb97c67ce704fb40abb6dd9971790652237e3 (patch) | |
| tree | ae0195ea9ae267742c755f71b5dc584f23c7a24e | |
| parent | 1356d6288bc85ae8784daef8d663acef9593d19a (diff) | |
| download | coreboot-211bb97c67ce704fb40abb6dd9971790652237e3.tar.xz | |
mb/google/eve: Update DPTF parameters
1) Set the critical temperature threshold to 100C to match changes
on other boards. This is intended to reduce DPTF-initiated thermal
shutdowns before it has had a chance to react.
2) Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.
BUG=b:67459049
BRANCH=eve
TEST=manual performance/power testing on Eve hardware
Change-Id: Ib660dcb25422fea0aa692fac5ba65b49808965ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/mainboard/google/eve/acpi/dptf.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl index 8937ee95d0..7dd42492ef 100644 --- a/src/mainboard/google/eve/acpi/dptf.asl +++ b/src/mainboard/google/eve/acpi/dptf.asl @@ -15,7 +15,7 @@ */ #define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_CRITICAL 100 #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Ambient" @@ -50,7 +50,7 @@ Name (CHPS, Package () { Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, /* CPU Effect on Ambient */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, |