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authorAaron Durbin <adurbin@chromium.org>2018-04-10 09:28:42 -0600
committerAaron Durbin <adurbin@chromium.org>2018-04-10 18:08:28 +0000
commit24de59702fc78d0a88dd895f87021dd6a5be70cf (patch)
treedde402be112a0eb29859427440caf53034c01c28
parente09ba47b8ba213e9a9d17c3fc0defb857e415100 (diff)
downloadcoreboot-24de59702fc78d0a88dd895f87021dd6a5be70cf.tar.xz
soc/intel/apollolake: fix SPI input clock speed
On APL and GLK the i2c blocks use 133MHz input clock, but the SPI blocks use a 100MHz input clock. Fix this so that the proper target frequencies can be hit on the SPI controllers. BUG=b:75306520 Change-Id: Iec36579894fa4633ac8d1035e6e7afec01af755f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
-rw-r--r--src/soc/intel/apollolake/Kconfig4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 19185eb411..029695d08a 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -161,11 +161,11 @@ config CPU_ADDR_BITS
config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
int
- default 133
+ default 100
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
- default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
+ default 133
config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL