mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY

Setting USBx_PORT_EMPTY is not a requirement anymore, since unset
devicetree settings default to 0 and the OC pin now only gets set when
the USB port is enabled (see CB:45112).

Thus, drop the setting from all devicetrees.

Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>

43 files changed, 0 insertions, 211 deletions

diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 6078741b70..95e2565a80 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -192,21 +192,13 @@ chip soc/intel/skylake
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"		# USB3_TYPE-A Port 2
 	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# USB-C Port 1
 	register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"	# M2 Port
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Disabled
 	register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)"	# Audio board
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Disabled
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Disabled
-	register "usb2_ports[9]" = "USB2_PORT_EMPTY"		# Disabled
-	register "usb2_ports[10]" = "USB2_PORT_EMPTY"		# Disabled
-	register "usb2_ports[11]" = "USB2_PORT_EMPTY"		# Disabled
 
 	# USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB-C Port 2
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3_TYPE-A Port 1
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3_TYPE-A Port 2
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB-C Port 1
-	register "usb3_ports[4]" = "USB3_PORT_EMPTY"		# Disabled
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"		# Disabled
 
 	register "SsicPortEnable" = "0"
 
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 13666ad3e9..363307b0db 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -32,16 +32,12 @@ chip soc/intel/jasperlake
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A1
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# Discrete Bluetooth
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Not Used
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Not Used
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# Integrated Bluetooth
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type-C Port C0
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type-C Port C1
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/1 Type-A Port A0
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/1 Type-A Port A1
-	register "usb3_ports[4]" = "USB3_PORT_EMPTY"		# Not Used
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"		# Not Used
 
 	register "SerialIoI2cMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
index 6937338931..90989d2b44 100644
--- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb
@@ -1,10 +1,7 @@
 chip soc/intel/jasperlake
 
 	# USB Port Configuration
-	register "usb2_ports[2]" = "USB2_PORT_EMPTY"	    # Not Used
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"	    # Not Used
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Camera
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"	    # Not Used
 
 	register "SerialIoI2cMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
index dfdcf5a4f3..52e689c177 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
@@ -38,16 +38,13 @@ chip soc/intel/tigerlake
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C Port 2
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"		# Ext USB Port 1 (Right)
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC1)"		# Ext USB Port 2 (Left)
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Camera
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 3042 (WWAN)
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# USH
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# BT
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Ext USB Port 1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Ext USB Port 2
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
 
 	# PCIe root port 7 (Card Reader), clock 4
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 851248d77d..ed7eb95d0d 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -152,9 +152,6 @@ chip soc/intel/cannonlake
 	register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)"	# Right Type-A Port 2
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# WWAN
 	register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)"	# Camera
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Left Type-C Port
@@ -162,7 +159,6 @@ chip soc/intel/cannonlake
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"	# Right Type-A Port 2
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Left Type-C Port 2
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index b42d917a3d..d9415212d7 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -153,12 +153,9 @@ chip soc/intel/skylake
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
 	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# H1
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Empty
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Empty
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Empty
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 5faf760ac9..bc29dc63af 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -248,7 +248,6 @@ chip soc/intel/skylake
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC1)"		# Type-A Rear
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"     # Type-A 2.0 / Debug
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# H1 (disconnected)
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Rear
diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
index 1d837934ac..3ca1648e0f 100644
--- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
@@ -49,15 +49,12 @@ chip soc/intel/skylake
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# Type-A Rear
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# HDMI Audio
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# None
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# H1 (disconnected)
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# HDMI
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Rear
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Rear
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Rear
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"	# None
 
 	register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"		# TPU
 	register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"		# TPM
diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb
index b1f3e8bb52..967a95a2c1 100644
--- a/src/mainboard/google/glados/variants/caroline/overridetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb
@@ -13,14 +13,10 @@ chip soc/intel/skylake
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-C Port (main)
 	register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)"	# Type-C Port (sub)
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"		# Empty
 	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Empty
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (main)
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (sub)
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Empty
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Empty
 
 	# PL2 override 15W
 	register "power_limits_config" = "{
diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb
index 7753dd4fb2..e77a2b4755 100644
--- a/src/mainboard/google/glados/variants/cave/overridetree.cb
+++ b/src/mainboard/google/glados/variants/cave/overridetree.cb
@@ -6,14 +6,10 @@ chip soc/intel/skylake
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C Port (board)
 	register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)"	# Type-C Port (flex)
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"		# Type-A Port 1
 	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Type-A Port 2
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C Port (board)
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C Port (flex)
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Type-A Port 1
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Type-A Port 2
 
 	# PL2 override 15W
 	register "power_limits_config" = "{
diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb
index 0e3972813a..2d60271d01 100644
--- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb
@@ -22,20 +22,12 @@ chip soc/intel/cannonlake
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 1
 	register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)"	# Type-A Port 0
-	register "usb2_ports[3]" = "USB2_PORT_EMPTY"	# Unused
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"	# WWAN
 	register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)"	# Camera
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# BT
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 0
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 1
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Port 0
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"	# Unused
-	register "usb3_ports[4]" = "USB3_PORT_EMPTY"	# WWAN
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index f13fcf8f9a..a4e07e9556 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -157,11 +157,8 @@ chip soc/intel/cannonlake
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 1
 	register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)"	# Type-A Port 0
 	register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)"	# Type-A Port 1
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# WWAN
 	register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)"	# Camera
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# BT
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 0
@@ -169,7 +166,6 @@ chip soc/intel/cannonlake
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Port 0
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Port 1
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
 
 	# Enable Root port 9(x4) for NVMe.
 	register "PcieRpEnable[8]" = "1"
diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
index 6bb1d94a69..25778f92cb 100644
--- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
@@ -66,9 +66,6 @@ chip soc/intel/cannonlake
 		.pre_emp_bias  = USB2_BIAS_28P15MV,
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # Type-A port 0
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "{
 		.enable = 1,
 		.ocpin = OC_SKIP,
diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
index a9e98d9f7e..c1bd1e4485 100644
--- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb
@@ -74,8 +74,6 @@ chip soc/intel/cannonlake
 		.pre_emp_bias  = USB2_BIAS_28P15MV,
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # PL2303
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "{
 		.enable = 1,
 		.ocpin = OC_SKIP,
diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
index e3dcbd5f87..50c6d0b1b1 100644
--- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
@@ -66,9 +66,6 @@ chip soc/intel/cannonlake
 		.pre_emp_bias  = USB2_BIAS_28P15MV,
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # Type-A port 0
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "{
 		.enable = 1,
 		.ocpin = OC_SKIP,
diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
index 6720ffce79..1b91e8f5ed 100644
--- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
@@ -27,21 +27,14 @@ chip soc/intel/cannonlake
 
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)"        # Type-C Port 0
 	register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)"        # Type-C Port 1
-	register "usb2_ports[2]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[3]" = "USB2_PORT_LONG(OC_SKIP)"    # SD CARD
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)"    # Camera
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"     # CnVi BT
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"     # Type-C Port 0
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"     # Type-C Port 1
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # World facing camera
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD
-	register "usb3_ports[4]" = "USB3_PORT_EMPTY"
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
index 3c184eb139..d6be1fb6fc 100644
--- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb
@@ -27,21 +27,11 @@ chip soc/intel/cannonlake
 
 	register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)"	# Type-C Port 0
 	register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)"	# Type-C Port 1
-	register "usb2_ports[2]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)"	# Camera
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# CnVi BT
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 0
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 1
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"
-	register "usb3_ports[4]" = "USB3_PORT_EMPTY"
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
index e206ea57e5..cf6046224c 100644
--- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb
@@ -48,7 +48,6 @@ chip soc/intel/cannonlake
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # Type-A Port 3
 	register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[5]" = "{
 		.enable = 1,
 		.ocpin = OC0,
@@ -57,9 +56,6 @@ chip soc/intel/cannonlake
 		.pre_emp_bias  = USB2_BIAS_28P15MV,
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # Type-A port 0
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "{
 		.enable = 1,
 		.ocpin = OC_SKIP,
@@ -74,7 +70,6 @@ chip soc/intel/cannonlake
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"     # Type-A Port 1
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"     # Type-A Port 0
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"            # Type-A Port 4
 
 	# Bitmap for Wake Enable on USB attach/detach
 	register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index fcbce27a82..0d9bf7237e 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -63,9 +63,6 @@ chip soc/intel/cannonlake
 		.pre_emp_bias  = USB2_BIAS_28P15MV,
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # Type-A port 0
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "{
 		.enable = 1,
 		.ocpin = OC_SKIP,
diff --git a/src/mainboard/google/hatch/variants/stryke/overridetree.cb b/src/mainboard/google/hatch/variants/stryke/overridetree.cb
index 329efa3b2a..536cd43de8 100644
--- a/src/mainboard/google/hatch/variants/stryke/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/stryke/overridetree.cb
@@ -18,20 +18,12 @@ chip soc/intel/cannonlake
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 0
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)"	# Type-C Port 1
 	register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)"	# Type-A Port 0
-	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)"	#Front Camera
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# BT
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 0
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# Type-C Port 1
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Port 0
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"
-	register "usb3_ports[4]" = "USB3_PORT_EMPTY"
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
index 24757b61c8..3320455ae3 100644
--- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
@@ -60,9 +60,6 @@ chip soc/intel/cannonlake
 		.pre_emp_bias  = USB2_BIAS_28P15MV,
 		.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP,
 	}" # Type-A port 0
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "{
 		.enable = 1,
 		.ocpin = OC_SKIP,
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index ce725f6ba8..4496dd9af6 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -149,17 +149,12 @@ chip soc/intel/skylake
 
 	# USB 2.0
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Empty
 	register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"	# Bluetooth
 	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Empty
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Empty
 
 	# USB 3.0
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Empty
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Empty
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 3197288573..14b8b09923 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -148,7 +148,6 @@ chip soc/intel/skylake
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A Port
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Empty
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 3606ae21d5..21f0b80274 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -159,18 +159,13 @@ chip soc/intel/skylake
 
 	# USB 2.0
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
-	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Empty
 	register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"	# Bluetooth
 	register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)"	# Type-C Port 2
 	register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)"	# pogo port
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Empty
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Empty
 
 	# USB 3.0
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Empty
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Empty
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 3587cda4be..0d31bca856 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -153,7 +153,6 @@ chip soc/intel/skylake
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Port
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Empty
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 2bddae2692..477166a422 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -148,7 +148,6 @@ chip soc/intel/skylake
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-C Port 1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-C Port 2
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A Port
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Empty
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 760e35146e..9a4c6dda10 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -132,8 +132,6 @@ chip soc/intel/cannonlake
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Left Type-C Port
 	register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)"	# Left Type-A Port
 	register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)"	# Right Type-A Port
-	register "usb2_ports[3]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)"	# Camera
 	register "usb2_ports[6]" = "{
 		.enable        = 1, \
@@ -151,8 +149,6 @@ chip soc/intel/cannonlake
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# Left Type-A Port
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"	# Right Type-A Port
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
-	register "usb3_ports[4]" = "USB3_PORT_EMPTY"
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 78f024cbf4..a76e2ed2e9 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -139,7 +139,6 @@ chip soc/intel/cannonlake
 	register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)"	# Right Type-A Port 1
 	register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)"	# Left Type-A Port
 	register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)"	# Right Type-A Port 2
-	register "usb2_ports[4]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)"	# Camera
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# WWAN
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# USH
@@ -151,7 +150,6 @@ chip soc/intel/cannonlake
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"	# Left Type-A Port
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"	# Right Type-A Port 2
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# WWAN
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index ffae2f0f9e..3e9e02ce53 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -55,9 +55,6 @@ chip soc/intel/tigerlake
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Cl
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
 	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Co
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
 
diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
index 2ef2e42634..e337a02293 100644
--- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
@@ -1,20 +1,10 @@
 chip soc/intel/tigerlake
-	register "usb2_ports[0]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Port 0
-	register "usb2_ports[2]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Port 1
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# Front Camera
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C Port 2
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# Reserve for CNVi BT
 
-	register "usb3_ports[0]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Port 0
-	register "usb3_ports[1]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Port 1
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Port 2
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
-
 	register "SaGv" = "SaGv_Disabled"
 
 	device domain 0 on
diff --git a/src/mainboard/google/volteer/variants/lindar/overridetree.cb b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
index 6f14622ecf..e16012d112 100644
--- a/src/mainboard/google/volteer/variants/lindar/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/lindar/overridetree.cb
@@ -1,20 +1,12 @@
 chip soc/intel/tigerlake
 	# USB Port Config
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
-	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb2_ports[2]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C C1
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
 	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C C0
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
-	register "usb3_ports[1]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
 
 	register "SaGv" = "SaGv_Disabled"
 	# I2C Port Config
diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb
index b18492423c..1dc6c2bff9 100644
--- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb
@@ -2,20 +2,12 @@ chip soc/intel/tigerlake
 
 	# USB Port Config
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
-	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb2_ports[2]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C C1
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
 	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A / Type-C C0
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
-	register "usb3_ports[1]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
 
 	register "SaGv" = "SaGv_Disabled"
 
diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb
index 42d3f2f441..a42664eaa4 100644
--- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb
@@ -10,12 +10,9 @@ chip soc/intel/tigerlake
 	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)"	# Type-A / Type-C Port 1
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Front Camera
 	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)"	# Type-A / Type-C Port 0
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A / Type-C Port 0
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A / Type-C Port 1
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
 
 	register "SaGv" = "SaGv_Disabled"
 
diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb
index 42d3f2f441..a42664eaa4 100644
--- a/src/mainboard/google/volteer/variants/todor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb
@@ -10,12 +10,9 @@ chip soc/intel/tigerlake
 	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)"	# Type-A / Type-C Port 1
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Front Camera
 	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)"	# Type-A / Type-C Port 0
-	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A / Type-C Port 0
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A / Type-C Port 1
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
 
 	register "SaGv" = "SaGv_Disabled"
 
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 6f282f05a4..1bd4bfec28 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -14,9 +14,6 @@ chip soc/intel/cannonlake
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
-	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
index a876994bfa..37b86c6be0 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
@@ -15,12 +15,10 @@ chip soc/intel/cannonlake
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"
 	register "usb2_ports[7]" = "USB2_PORT_MID(OC1)"
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"
 	register "usb2_ports[10]" = "USB2_PORT_MID(OC3)"
 	register "usb2_ports[11]" = "USB2_PORT_MID(OC6)"
 	register "usb2_ports[12]" = "USB2_PORT_MID(OC6)"
-	register "usb2_ports[13]" = "USB2_PORT_EMPTY"
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)"
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index 4bcfc99083..0754c0735e 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -93,8 +93,6 @@ chip soc/intel/skylake
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"	# TYPE-A Port
-	register "usb3_ports[4]" = "USB3_PORT_EMPTY"	# Disabled
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"	# Disabled
 
 	register "SsicPortEnable" = "1" # Enable SSIC for WWAN
 
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 2dd65c4e8d..d4390b0b29 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -29,8 +29,6 @@ chip soc/intel/tigerlake
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Not used
-	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# USB3/USB2 Flex Connector
 
 	# CPU replacement check
 	register "CpuReplacementCheck" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index a79bf80073..7a5cae196d 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -22,14 +22,10 @@ chip soc/intel/tigerlake
 	register "usb2_ports[3]" = "USB2_PORT_MID(OC3)"		# USB3/2 Type A port1
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# Type-C Port2
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"		# Type-C Port3
-	register "usb3_ports[6]" = "USB3_PORT_EMPTY"		# Not used
-	register "usb3_ports[7]" = "USB3_PORT_EMPTY"		# Not used
-	register "usb3_ports[8]" = "USB3_PORT_EMPTY"		# Not used
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"		# CNVi/BT
 
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port1
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port2
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Not used
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/USB2 Flex Connector
 
 	# CPU replacement check
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
index 7759b57f27..01b9537e13 100644
--- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
+++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
@@ -118,8 +118,6 @@ chip soc/intel/cannonlake
 	# USB OC5-7: not connected
 	# BMC
 	register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)"
-	# unused
-	register "usb2_ports[11]" = "USB2_PORT_EMPTY"
 	# piggy-back
 	register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
 	# M2 key E
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index a5b3638220..2a4b1e9ffd 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -177,18 +177,12 @@ chip soc/intel/skylake
 	register "usb2_ports[5]"  = "USB2_PORT_SHORT(OC_SKIP)"	# TYPE-A Port
 	register "usb2_ports[6]"  = "USB2_PORT_SHORT(OC_SKIP)"	# TYPE-A Port
 	register "usb2_ports[7]"  = "USB2_PORT_SHORT(OC_SKIP)"	# mPCIe slot
-	register "usb2_ports[8]"  = "USB2_PORT_EMPTY"		# Disabled
-	register "usb2_ports[9]"  = "USB2_PORT_EMPTY"		# Disabled
-	register "usb2_ports[10]" = "USB2_PORT_EMPTY"		# Disabled
-	register "usb2_ports[11]" = "USB2_PORT_EMPTY"		# Disabled
 
 	# USB 3.0 enable ports 1-4, disable ports 5-6
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# TYPE-A Port
-	register "usb3_ports[4]" = "USB3_PORT_EMPTY"		# Disabled
-	register "usb3_ports[5]" = "USB3_PORT_EMPTY"		# Disabled
 
 	register "SerialIoDevMode" = "{ \
 		[PchSerialIoIndexI2C0]  = PchSerialIoDisabled, \
diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb
index b85e10f402..497a4cca4d 100644
--- a/src/mainboard/purism/librem_whl/devicetree.cb
+++ b/src/mainboard/purism/librem_whl/devicetree.cb
@@ -82,27 +82,14 @@ chip soc/intel/cannonlake
 	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A front right upper
 	register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)"	# Type-C rear
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# m.2-2230/Bluetooth
-	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# NC
-	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# NC
 	register "usb2_ports[9]" = "USB2_PORT_MID(OC2)"		# Type-A rear lower
-	register "usb2_ports[10]" = "USB2_PORT_EMPTY"		# NC
-	register "usb2_ports[11]" = "USB2_PORT_EMPTY"		# NC
-	register "usb2_ports[12]" = "USB2_PORT_EMPTY"		# NC
-	register "usb2_ports[13]" = "USB2_PORT_EMPTY"		# NC
-	register "usb2_ports[14]" = "USB2_PORT_EMPTY"		# NC
-	register "usb2_ports[15]" = "USB2_PORT_EMPTY"		# NC
 
 	# USB3
 	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A front left lower
-	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# NC
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"	# Type-C rear
 	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A rear lower
 	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A rear upper
-	register "usb3_ports[6]" = "USB3_PORT_EMPTY"		# NC
-	register "usb3_ports[7]" = "USB3_PORT_EMPTY"		# NC
-	register "usb3_ports[8]" = "USB3_PORT_EMPTY"		# NC
-	register "usb3_ports[9]" = "USB3_PORT_EMPTY"		# NC
 
 	# All SRCCLKREQ pins mapped directly
 	register "PcieClkSrcClkReq[0]" = "0"
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index bbc52db5e7..dd0e520365 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -39,36 +39,6 @@ chip soc/intel/skylake
 	# superspeed_inter-chip_supplement (SSIC) disabled
 	register "SsicPortEnable" = "0"
 
-	# USB
-	register "usb2_ports" = "{
-		[0]	= USB2_PORT_EMPTY,
-		[1]	= USB2_PORT_EMPTY,
-		[2]	= USB2_PORT_EMPTY,
-		[3]	= USB2_PORT_EMPTY,
-		[4]	= USB2_PORT_EMPTY,
-		[5]	= USB2_PORT_EMPTY,
-		[6]	= USB2_PORT_EMPTY,
-		[7]	= USB2_PORT_EMPTY,
-		[8]	= USB2_PORT_EMPTY,
-		[9]	= USB2_PORT_EMPTY,
-		[10]	= USB2_PORT_EMPTY,
-		[11]	= USB2_PORT_EMPTY,
-		[12]	= USB2_PORT_EMPTY,
-		[13]	= USB2_PORT_EMPTY,
-	}"
-	register "usb3_ports" = "{
-		[0]	= USB3_PORT_EMPTY,
-		[1]	= USB3_PORT_EMPTY,
-		[2]	= USB3_PORT_EMPTY,
-		[3]	= USB3_PORT_EMPTY,
-		[4]	= USB3_PORT_EMPTY,
-		[5]	= USB3_PORT_EMPTY,
-		[6]	= USB3_PORT_EMPTY,
-		[7]	= USB3_PORT_EMPTY,
-		[8]	= USB3_PORT_EMPTY,
-		[9]	= USB3_PORT_EMPTY,
-	}"
-
 	# LPC
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"