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authorStefan Reinauer <stepan@coreboot.org>2010-12-11 22:14:44 +0000
committerStefan Reinauer <stepan@openbios.org>2010-12-11 22:14:44 +0000
commit2a27b20226a2fd593bfd5f6a0eee45418233fe04 (patch)
tree950aa542d9266c1cb004d2346062609c37ed16b3
parent2b9070a610132eaf61dca67e7713c082903fffef (diff)
downloadcoreboot-2a27b20226a2fd593bfd5f6a0eee45418233fe04.tar.xz
factor out cpu power management base into a separate file. And fix a bug in
model_1067x Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/cpu/intel/model_1067x/model_1067x_init.c3
-rw-r--r--src/cpu/intel/model_106cx/model_106cx_init.c5
-rw-r--r--src/cpu/intel/model_6ex/model_6ex_init.c10
-rw-r--r--src/cpu/intel/model_6fx/model_6fx_init.c10
-rw-r--r--src/cpu/intel/speedstep/acpi.c3
-rw-r--r--src/include/cpu/intel/speedstep.h31
6 files changed, 38 insertions, 24 deletions
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 46a54e597d..ca2b960b8b 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -28,6 +28,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
@@ -98,8 +99,6 @@ static void enable_vmx(void)
#define PMG_IO_BASE_ADDR 0xe3
#define PMG_IO_CAPTURE_ADDR 0xe4
-#define PMB0_BASE 0x580
-#define PMB1_BASE 0x800
#define CST_RANGE 2
static void configure_c_states(void)
{
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index f83a0bbbf0..2e38e775a6 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -26,6 +26,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
@@ -82,9 +83,7 @@ static void enable_vmx(void)
#define PMG_CST_CONFIG_CONTROL 0xe2
#define PMG_IO_BASE_ADDR 0xe3
#define PMG_IO_CAPTURE_ADDR 0xe4
-#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */
-#define PMB1 0x0 /* IO port that triggers SMI once cores are in the same state.
- See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */
+
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
{
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 384b2bf68b..eee651a207 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -29,6 +29,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/hyperthreading.h>
+#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <usbdebug.h>
@@ -80,15 +81,6 @@ static void enable_vmx(void)
#define PMG_IO_BASE_ADDR 0xe3
#define PMG_IO_CAPTURE_ADDR 0xe4
-/* MWAIT coordination I/O base address. This must match
- * the \_PR_.CPU0 PM base address.
- */
-#define PMB0_BASE 0x510
-
-/* PMB1: I/O port that triggers SMI once cores are in the same state.
- * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
- */
-#define PMB1_BASE 0x800
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
{
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 0944aab955..a3939c91f7 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -28,6 +28,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
@@ -94,15 +95,6 @@ static void enable_vmx(void)
#define PMG_IO_BASE_ADDR 0xe3
#define PMG_IO_CAPTURE_ADDR 0xe4
-/* MWAIT coordination I/O base address. This must match
- * the \_PR_.CPU0 PM base address.
- */
-#define PMB0_BASE 0x510
-
-/* PMB1: I/O port that triggers SMI once cores are in the same state.
- * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
- */
-#define PMB1_BASE 0x800
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
{
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 954b669515..48e1a3cedc 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -26,6 +26,7 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/acpi.h>
+#include <cpu/intel/speedstep.h>
#include <device/device.h>
// XXX: PSS table values for power consumption are for Merom only
@@ -64,7 +65,7 @@ static int get_fsb(void)
void generate_cpu_entries(void)
{
int len_pr, len_ps;
- int coreID, cpuID, pcontrol_blk=0x510, plen=6;
+ int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
msr_t msr;
int totalcores = determine_total_number_of_cores();
int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
new file mode 100644
index 0000000000..0fa5244181
--- /dev/null
+++ b/src/include/cpu/intel/speedstep.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* MWAIT coordination I/O base address. This must match
+ * the \_PR_.CPU0 PM base address.
+ */
+#define PMB0_BASE 0x510
+
+/* PMB1: I/O port that triggers SMI once cores are in the same state.
+ * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
+ */
+#define PMB1_BASE 0x800
+