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authorCole Nelson <colex.nelson@intel.com>2018-06-12 09:56:24 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-06-14 09:25:57 +0000
commit2b69b21c2db20ddce1f04e72b3eaa1d624540845 (patch)
tree022abacdf853c5d23f1e1f740fda0fc2da292c12
parentc38960d7f3fd929fa916ac696fcfb8a7b5534c8d (diff)
downloadcoreboot-2b69b21c2db20ddce1f04e72b3eaa1d624540845.tar.xz
soc/intel/common: defines constant for C1E enable mask
Register 0x1fc (MSR_POWER_CTL) deserves a proper mask for the C1E enable bit. Define POWER_CTL_C1E_MASK to be used subsequently. Change-Id: I7a5408f6678f56540929b7811764845b6dad1149 Signed-off-by: Cole Nelson <colex.nelson@intel.com> Reviewed-on: https://review.coreboot.org/27035 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/common/block/include/intelblocks/msr.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 22e8862e98..e1fc431f3a 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -72,6 +72,7 @@
#define PRMRR_PHYS_MASK_LOCK (1 << 10)
#define PRMRR_PHYS_MASK_VALID (1 << 11)
#define MSR_POWER_CTL 0x1fc
+#define POWER_CTL_C1E_MASK (1 << 1)
#define MSR_EVICT_CTL 0x2e0
#define MSR_SGX_OWNEREPOCH0 0x300
#define MSR_SGX_OWNEREPOCH1 0x301