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| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-11 00:24:40 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-11 09:19:05 +0000 |
| commit | 2f572dd964db1ca475af38d4b8592001dd22ed9e (patch) | |
| tree | d9a3a5c8861362a22e037bfe859abc7cbc858f43 | |
| parent | 8084b3856852f3fb3905e0fe4957b08518095d38 (diff) | |
| download | coreboot-2f572dd964db1ca475af38d4b8592001dd22ed9e.tar.xz | |
mb/hp/folio_9480m: Drop `sata_ahci` from devtree
Commit 8084b38568 (sb/intel/lynxpoint/sata: Always use AHCI mode)
dropped the devtree option, but missed this recently-added mainboard.
Change-Id: I6ab3a763c0bcd7431193c48e473639589b1a1e1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/mainboard/hp/folio_9480m/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index bd81d38197..140aa844f5 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -36,7 +36,6 @@ chip northbridge/intel/haswell register "gen2_dec" = "0x000c0101" register "gen4_dec" = "0x000402e9" register "xhci_default" = "1" - register "sata_ahci" = "1" register "sata_port1_gen3_dtle" = "0x6" # SATA(1), M.2(3) register "sata_port_map" = "0xa" |