summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorBora Guvendik <bora.guvendik@intel.com>2020-03-09 18:20:07 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-30 08:43:09 +0000
commit3a1a037231ddb5cdc03d0e147c2335de0f1c8ad6 (patch)
tree9b1f982991edb60eac011f3824ebb4d4bcf244da
parent97bd2a7f33a784b63b8ede4efc23f39d4dfce37b (diff)
downloadcoreboot-3a1a037231ddb5cdc03d0e147c2335de0f1c8ad6.tar.xz
mb/google/deltaur: add deltaur mainboard initial support
Created a new Google baseboard using Tiger Lake named deltaur, taking volteer as a starting point. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
-rw-r--r--src/mainboard/google/deltaur/Kconfig83
-rw-r--r--src/mainboard/google/deltaur/Kconfig.name9
-rw-r--r--src/mainboard/google/deltaur/Makefile.inc30
-rw-r--r--src/mainboard/google/deltaur/board_info.txt6
-rw-r--r--src/mainboard/google/deltaur/bootblock.c26
-rw-r--r--src/mainboard/google/deltaur/chromeos.c117
-rw-r--r--src/mainboard/google/deltaur/chromeos.fmd48
-rw-r--r--src/mainboard/google/deltaur/dsdt.asl51
-rw-r--r--src/mainboard/google/deltaur/ec.c14
-rw-r--r--src/mainboard/google/deltaur/mainboard.c35
-rw-r--r--src/mainboard/google/deltaur/smihandler.c26
-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/Makefile.inc11
-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/devicetree.cb6
-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/gpio.c47
-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h14
-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h13
-rw-r--r--src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h24
-rw-r--r--src/mainboard/google/deltaur/variants/deltan/Makefile.inc9
-rw-r--r--src/mainboard/google/deltaur/variants/deltan/gpio.c31
-rw-r--r--src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h15
-rw-r--r--src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h14
-rw-r--r--src/mainboard/google/deltaur/variants/deltan/overridetree.cb6
-rw-r--r--src/mainboard/google/deltaur/variants/deltaur/Makefile.inc9
-rw-r--r--src/mainboard/google/deltaur/variants/deltaur/gpio.c31
-rw-r--r--src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h15
-rw-r--r--src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h14
-rw-r--r--src/mainboard/google/deltaur/variants/deltaur/overridetree.cb6
27 files changed, 710 insertions, 0 deletions
diff --git a/src/mainboard/google/deltaur/Kconfig b/src/mainboard/google/deltaur/Kconfig
new file mode 100644
index 0000000000..dcbe5ecbad
--- /dev/null
+++ b/src/mainboard/google/deltaur/Kconfig
@@ -0,0 +1,83 @@
+config BOARD_GOOGLE_BASEBOARD_DELTAUR
+ def_bool n
+ select BOARD_ROMSIZE_KB_32768
+ select DRIVERS_I2C_GENERIC
+ select DRIVERS_INTEL_ISH
+ select DRIVERS_SPI_ACPI
+ select EC_GOOGLE_WILCO
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_I2C_TPM_CR50
+ select MAINBOARD_HAS_TPM2
+ select MAINBOARD_USES_IFD_EC_REGION
+ select SOC_INTEL_TIGERLAKE
+ select SYSTEM_TYPE_LAPTOP
+
+if BOARD_GOOGLE_BASEBOARD_DELTAUR
+
+config CHROMEOS
+ bool
+ default y
+ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+ select GBB_FLAG_FORCE_DEV_SWITCH_ON
+ select GBB_FLAG_FORCE_DEV_BOOT_USB
+ select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config DEVICETREE
+ string
+ default "variants/baseboard/devicetree.cb"
+
+config DRIVER_TPM_I2C_BUS
+ hex
+ default 0x3
+
+config DRIVER_TPM_I2C_ADDR
+ hex
+ default 0x50
+
+config OVERRIDE_DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_DIR
+ string
+ default "google/deltaur"
+
+config MAINBOARD_FAMILY
+ string
+ default "Google_Deltaur"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Deltan" if BOARD_GOOGLE_DELTAN
+ default "Deltaur" if BOARD_GOOGLE_DELTAUR
+
+config MAX_CPUS
+ int
+ default 8
+
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 23 # GPE0_DW0_23 (GPP_C23)
+
+config UART_FOR_CONSOLE
+ int
+ default 2
+
+config VARIANT_DIR
+ string
+ default "deltan" if BOARD_GOOGLE_DELTAN
+ default "deltaur" if BOARD_GOOGLE_DELTAUR
+
+config VBOOT
+ select HAS_RECOVERY_MRC_CACHE
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+ select VBOOT_LID_SWITCH
+
+endif # BOARD_GOOGLE_BASEBOARD_DELTAUR
diff --git a/src/mainboard/google/deltaur/Kconfig.name b/src/mainboard/google/deltaur/Kconfig.name
new file mode 100644
index 0000000000..5c4c12b479
--- /dev/null
+++ b/src/mainboard/google/deltaur/Kconfig.name
@@ -0,0 +1,9 @@
+comment "Deltaur"
+
+config BOARD_GOOGLE_DELTAN
+ bool "-> Deltan"
+ select BOARD_GOOGLE_BASEBOARD_DELTAUR
+
+config BOARD_GOOGLE_DELTAUR
+ bool "-> Deltaur"
+ select BOARD_GOOGLE_BASEBOARD_DELTAUR
diff --git a/src/mainboard/google/deltaur/Makefile.inc b/src/mainboard/google/deltaur/Makefile.inc
new file mode 100644
index 0000000000..a913c75da2
--- /dev/null
+++ b/src/mainboard/google/deltaur/Makefile.inc
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+bootblock-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += ec.c
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += mainboard.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-y += ec.c
+
+smm-y += smihandler.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+subdirs-y += spd
diff --git a/src/mainboard/google/deltaur/board_info.txt b/src/mainboard/google/deltaur/board_info.txt
new file mode 100644
index 0000000000..897a63b04b
--- /dev/null
+++ b/src/mainboard/google/deltaur/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Deltaur
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/deltaur/bootblock.c b/src/mainboard/google/deltaur/bootblock.c
new file mode 100644
index 0000000000..c2cffd064f
--- /dev/null
+++ b/src/mainboard/google/deltaur/bootblock.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+#include <ec/google/wilco/bootblock.h>
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static void early_config_gpio(void)
+{
+ const struct pad_config *early_gpio_table;
+ size_t num_gpios = 0;
+
+ early_gpio_table = variant_early_gpio_table(&num_gpios);
+ gpio_configure_pads(early_gpio_table, num_gpios);
+}
+
+void bootblock_mainboard_init(void)
+{
+ early_config_gpio();
+ wilco_ec_early_init();
+}
diff --git a/src/mainboard/google/deltaur/chromeos.c b/src/mainboard/google/deltaur/chromeos.c
new file mode 100644
index 0000000000..128378828a
--- /dev/null
+++ b/src/mainboard/google/deltaur/chromeos.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <security/tpm/tss.h>
+#include <device/device.h>
+#include <intelblocks/pmclib.h>
+#include <soc/pmc.h>
+#include <soc/pci_devs.h>
+
+
+enum rec_mode_state {
+ REC_MODE_UNINITIALIZED,
+ REC_MODE_NOT_REQUESTED,
+ REC_MODE_REQUESTED,
+};
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {-1, ACTIVE_HIGH, 0, "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+static int cros_get_gpio_value(int type)
+{
+ const struct cros_gpio *cros_gpios;
+ size_t i, num_gpios = 0;
+
+ cros_gpios = variant_cros_gpios(&num_gpios);
+
+ for (i = 0; i < num_gpios; i++) {
+ const struct cros_gpio *gpio = &cros_gpios[i];
+ if (gpio->type == type) {
+ int state = gpio_get(gpio->gpio_num);
+ if (gpio->polarity == CROS_GPIO_ACTIVE_LOW)
+ return !state;
+ else
+ return state;
+ }
+ }
+ return 0;
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ const struct cros_gpio *cros_gpios;
+ size_t num_gpios = 0;
+
+ cros_gpios = variant_cros_gpios(&num_gpios);
+
+ chromeos_acpi_gpio_generate(cros_gpios, num_gpios);
+}
+
+int get_write_protect_state(void)
+{
+ return cros_get_gpio_value(CROS_GPIO_WP);
+}
+
+int get_recovery_mode_switch(void)
+{
+ static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED;
+ enum rec_mode_state state = REC_MODE_NOT_REQUESTED;
+ uint8_t cr50_state = 0;
+
+ /* Check cached state, since TPM will only tell us the first time */
+ if (saved_rec_mode != REC_MODE_UNINITIALIZED)
+ return saved_rec_mode == REC_MODE_REQUESTED;
+
+ /*
+ * Read one-time recovery request from cr50 in verstage only since
+ * the TPM driver won't be set up in time for other stages like romstage
+ * and the value from the TPM would be wrong anyway since the verstage
+ * read would have cleared the value on the TPM.
+ *
+ * The TPM recovery request is passed between stages through vboot data
+ * or cbmem depending on stage.
+ */
+ if (ENV_VERSTAGE &&
+ tlcl_cr50_get_recovery_button(&cr50_state) == TPM_SUCCESS &&
+ cr50_state)
+ state = REC_MODE_REQUESTED;
+
+ /* Read state from the GPIO controlled by servo. */
+ if (cros_get_gpio_value(CROS_GPIO_REC))
+ state = REC_MODE_REQUESTED;
+
+ /* Store the state in case this is called again in verstage. */
+ saved_rec_mode = state;
+
+ return state == REC_MODE_REQUESTED;
+}
+
+int get_lid_switch(void)
+{
+ return 1;
+}
+
+void mainboard_prepare_cr50_reset(void)
+{
+ /* Ensure system powers up after CR50 reset */
+ if (ENV_RAMSTAGE)
+ pmc_soc_set_afterg3_en(true);
+}
diff --git a/src/mainboard/google/deltaur/chromeos.fmd b/src/mainboard/google/deltaur/chromeos.fmd
new file mode 100644
index 0000000000..d0cf8e92f8
--- /dev/null
+++ b/src/mainboard/google/deltaur/chromeos.fmd
@@ -0,0 +1,48 @@
+FLASH@0xfe000000 0x2000000 {
+ SI_ALL@0x0 0x604000 {
+ SI_DESC@0x0 0x1000
+ SI_EC@0x1000 0x100000
+ SI_ME@0x101000 0x4ff000
+ SI_PDR(PRESERVE)@0x600000 0x4000
+ }
+ SI_BIOS@0x604000 0x19fc000 {
+ RW_DIAG@0x0 0x10cc000 {
+ RW_LEGACY(CBFS)@0x0 0x10bc000
+ DIAG_NVRAM@0x10bc000 0x10000
+ }
+ RW_SECTION_A@0x10cc000 0x280000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x26ffc0
+ RW_FWID_A@0x27ffc0 0x40
+ }
+ RW_SECTION_B@0x134c000 0x280000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x26ffc0
+ RW_FWID_B@0x27ffc0 0x40
+ }
+ RW_MISC@0x15cc000 0x30000 {
+ UNIFIED_MRC_CACHE@0x0 0x20000 {
+ RECOVERY_MRC_CACHE@0x0 0x10000
+ RW_MRC_CACHE@0x10000 0x10000
+ }
+ RW_ELOG(PRESERVE)@0x20000 0x4000
+ RW_SHARED@0x24000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD(PRESERVE)@0x28000 0x2000
+ RW_NVRAM(PRESERVE)@0x2a000 0x6000
+ }
+ WP_RO@0x15fc000 0x400000 {
+ RO_VPD(PRESERVE)@0x0 0x4000
+ RO_UNUSED@0x4000 0xc000
+ RO_SECTION@0x10000 0x3f0000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0x3000
+ COREBOOT(CBFS)@0x4000 0x3ec000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl
new file mode 100644
index 0000000000..b6bc8e4248
--- /dev/null
+++ b/src/mainboard/google/deltaur/dsdt.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <arch/acpi.h>
+#include "variant/ec.h"
+#include "variant/gpio.h"
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI v2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 /* OEM revision */
+)
+{
+ #include <soc/intel/tigerlake/acpi/platform.asl>
+
+ /* global NVS and variables */
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/tigerlake/acpi/southbridge.asl>
+ }
+ }
+
+ /* Chrome OS specific */
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* VPD support */
+ #include <vendorcode/google/chromeos/acpi/vpd.asl>
+
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/wilco/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/wilco/acpi/ec.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/google/deltaur/ec.c b/src/mainboard/google/deltaur/ec.c
new file mode 100644
index 0000000000..5dd7237bdd
--- /dev/null
+++ b/src/mainboard/google/deltaur/ec.c
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <console/console.h>
+#include <ec/google/wilco/commands.h>
+#include <variant/ec.h>
+
+void mainboard_post(uint8_t value)
+{
+ wilco_ec_save_post_code(value);
+}
diff --git a/src/mainboard/google/deltaur/mainboard.c b/src/mainboard/google/deltaur/mainboard.c
new file mode 100644
index 0000000000..eca5ee8e78
--- /dev/null
+++ b/src/mainboard/google/deltaur/mainboard.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <variant/gpio.h>
+
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+static void mainboard_chip_init(void *chip_info)
+{
+ const struct pad_config *base_pads;
+ const struct pad_config *override_pads;
+ size_t base_num, override_num;
+
+ base_pads = variant_base_gpio_table(&base_num);
+ override_pads = variant_override_gpio_table(&override_num);
+
+ gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_chip_init,
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/deltaur/smihandler.c b/src/mainboard/google/deltaur/smihandler.c
new file mode 100644
index 0000000000..fc68a22a52
--- /dev/null
+++ b/src/mainboard/google/deltaur/smihandler.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/wilco/smm.h>
+#include <intelblocks/smihandler.h>
+#include <variant/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+ wilco_ec_smi_espi();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ wilco_ec_smi_sleep(slp_typ);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ wilco_ec_smi_apmc(apmc);
+ return 0;
+}
diff --git a/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc b/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000000..937cb4628f
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/baseboard/Makefile.inc
@@ -0,0 +1,11 @@
+##
+## This file is part of the coreboot project.
+##
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
+
+verstage-y += gpio.c
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
new file mode 100644
index 0000000000..a4031622ef
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/tigerlake
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+end
diff --git a/src/mainboard/google/deltaur/variants/baseboard/gpio.c b/src/mainboard/google/deltaur/variants/baseboard/gpio.c
new file mode 100644
index 0000000000..3951ce0b5d
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/baseboard/gpio.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+
+};
+
+const struct pad_config *__weak variant_base_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config *__weak variant_override_gpio_table(size_t *num)
+{
+ *num = 0;
+ return NULL;
+}
+
+const struct pad_config *__weak variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+
+};
+
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000000..3825cc8824
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef __MAINBOARD_EC_H__
+#define __MAINBOARD_EC_H__
+
+
+
+
+
+#endif /* __MAINBOARD_EC_H__ */
diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000000..8411900243
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,13 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpio.h>
+
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..1d8a934ecc
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <stddef.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct pad_config *variant_base_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_override_gpio_table(size_t *num);
+
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc
new file mode 100644
index 0000000000..ea0d5f0157
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc
@@ -0,0 +1,9 @@
+##
+## This file is part of the coreboot project.
+##
+##
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+bootblock-y += gpio.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/deltaur/variants/deltan/gpio.c b/src/mainboard/google/deltaur/variants/deltan/gpio.c
new file mode 100644
index 0000000000..30315bbc2e
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltan/gpio.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h
new file mode 100644
index 0000000000..7044eebf37
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/ec.h
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+
+#endif
diff --git a/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h b/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h
new file mode 100644
index 0000000000..a1e37894e8
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltan/include/variant/gpio.h
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+/* Copied from baseboard and may need to change for the new variant. */
+
+#endif
diff --git a/src/mainboard/google/deltaur/variants/deltan/overridetree.cb b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb
new file mode 100644
index 0000000000..32204c58e7
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltan/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/tigerlake
+
+ device domain 0 on
+ end
+
+end
diff --git a/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc
new file mode 100644
index 0000000000..ea0d5f0157
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc
@@ -0,0 +1,9 @@
+##
+## This file is part of the coreboot project.
+##
+##
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+bootblock-y += gpio.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/deltaur/variants/deltaur/gpio.c b/src/mainboard/google/deltaur/variants/deltaur/gpio.c
new file mode 100644
index 0000000000..30315bbc2e
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltaur/gpio.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
diff --git a/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h b/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h
new file mode 100644
index 0000000000..7044eebf37
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltaur/include/variant/ec.h
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef __VARIANT_EC_H__
+#define __VARIANT_EC_H__
+
+#include <baseboard/ec.h>
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+
+#endif
diff --git a/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h b/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h
new file mode 100644
index 0000000000..a1e37894e8
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltaur/include/variant/gpio.h
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <baseboard/gpio.h>
+
+/* Copied from baseboard and may need to change for the new variant. */
+
+#endif
diff --git a/src/mainboard/google/deltaur/variants/deltaur/overridetree.cb b/src/mainboard/google/deltaur/variants/deltaur/overridetree.cb
new file mode 100644
index 0000000000..32204c58e7
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltaur/overridetree.cb
@@ -0,0 +1,6 @@
+chip soc/intel/tigerlake
+
+ device domain 0 on
+ end
+
+end